03-03-2021 09:46 AM
Hello, I am an FPGA newbie. Just got a question regarding Xilinx DMA IP. My project involves reading data from an XADC at a frequency above 1 kHz. Right now, I am using a MicroBlaze with a timer interrupt to do this. However, the MicroBlaze also runs the lwIP library to implement a TCP/IP stack on it, and the reading of the XADC from the MicroBlaze seems to overwhelm the MicroBlaze as the frequency increases above 500Hz. So, I am trying to offload the XADC reading to a DMA IP that moves data from the XADC to a FIFO. The trouble I am having right now is I couldn't find a way to trigger the DMA IP transfer without the intervention of the Microblaze at the end of each transfer. I couldn't find a way to set a delay between each transfer either ( the delay here is to make sure I am collecting samples from the XADC at a frequency below the sampling frequency of the XADC). It would be perfect if the Microblaze could set up the DMA only at the beginning then the DMA will automatically run the configured transfer every 100ms without the intervention from the Microblaze. Does anyone know if this is doable with Xilinx DMA IP or any other DMA?
03-03-2021 08:58 PM
You can try with Cyclic DMA mode which fetches and processes the same BDs without interruption.
Please refer to PG021, page no.74 for more details.
03-04-2021 01:50 PM
Thanks for your suggestion, I planned to use it too, however, I could not find a way to insert a delay between each cycle. My intention is to have the DMA read the XADC at a certain frequency for a certain number of times. The idea is to record the data from the XADC like we record video from the camera by capturing images at a certain rate. If we could control the acquisition rate, we should be able to replay the data with the right timescale (like when we replay the video if we know it is recorded at 24Hz, and we set the playback to play at 24Hz, the video will look like normal, not fast forward, or slow motion). Is there a way to control this delay on the DMA, you think?