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zigenz
Visitor
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Registered: ‎04-16-2019

Trouble getting basic PS/PL comms going

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Hi there,

Whilst I've done a reasonable amount of HDL before, I've only recently ventured into the Xilinx Ultrascale+ world via the Avnet Ultra96 V2 board.  I've put together a few purely PL projects on the board, but now want to take the next step; I'd like to have a basic standalone C application performing some calculations and pushing the outputs to the PL via AXI4-Lite 32-bit register transfers.

As a first test, I just wanted to create a vanilla AXI4-Lite peripheral, hook it up, and confirm that I can at least enact the transfer from the PS side - unfortunately, most of the online tutorials / samples use older versions of Vivado, specifically they have a "Launch SDK" facility in the File menu, which doesn't exist in Vivado v2020.2.

I've managed to get all the bits seemingly hooked together, but when I perform an Xil_Out32() to any element, I end up in the asm_vectors.S file at the following point (lines 185-187).

 

	b	_boot
.org (VBAR + 0x200)
	b	SynchronousInterruptHandler

 

The following is the workflow I am using.  I am hoping someone can point out my folly and put me on the right track!

1. Create a new RTL project using the Ultra96V2 SBC board profile from Avnet.

2. Create a block design, add the ZYNQ Ultrascale+ part, and run Block Automation.  This creates two FPD AXI Master interfaces (HPM0 and HPM 1).  For simplicity, I go into the block design and remove the second master.  At this point, my block diagram looks like this:

zigenz_0-1620307849225.png

3. I then enter the Tools>Create and Package New IP menu, select "Create AXI4 Peripheral", accept defaults, and then add the IP to the reposiitory, i.e.: 

zigenz_1-1620308088561.png

4. I add the IP to the block diagram and run Connection Automation with "Auto" for all options.  At this point, my block diagram is as shown below:

zigenz_2-1620308217177.png

5. I create an HDL Wrapper for my block diagram, Generate Output Products, Generate Bitstream, and Export Hardware (with Include Bitstream selected).

6. At this point I switch over to Vitis (v2020.2), change the workspace directory to the project root, and launch.

7. I create an Application Project, with the platform derived from the HDL project XSA file, i.e.:

zigenz_0-1620309153745.png

8. Accept Domain defaults and apply the "Hello World" template.

9. I modify the main as follows:

 

#include <stdio.h>
#include "platform.h"
#include "xil_printf.h"
#include "xil_io.h"

int main()
{
    init_platform();

    Xil_Out32( XPAR_MYIP_0_S00_AXI_BASEADDR, 0x00000000 );

    print("Hello World\n\r");
    print("Successfully ran Hello World application");
    cleanup_platform();
    return 0;
}

 

10. I build the application by right-clicking "ps_pl_comms_test [standalone_psu_cortexa53_0]" in the Explorer view and selecting "Build Project", i.e.:

zigenz_1-1620309776303.png

 

11. In the Assistant view, I right click the "Debug" item under the "ps_pl_comms_test [Application]" tree item, and select "Debug>Launch On Hardware (Single Application Debug)".

12. I step through the code, and when I get to the Xil_Out32() function, I get the exception as described earlier.

The XCST console log is below (I think there are a couple of runs in there):

 

xsct% attempting to launch hw_server

****** Xilinx hw_server v2020.2
  **** Build date : Nov 18 2020 at 09:50:49
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

INFO: hw_server application started
INFO: Use Ctrl-C to exit hw_server application

INFO: To connect to this hw_server instance use url: TCP:127.0.0.1:3121


initializing
  0%    0MB   0.0MB/s  ??:?? ETA
 20%    1MB   2.2MB/s  ??:?? ETA
 36%    1MB   1.9MB/s  ??:?? ETA
 51%    2MB   1.8MB/s  ??:?? ETA
 67%    3MB   1.8MB/s  ??:?? ETA
 84%    4MB   1.7MB/s  ??:?? ETA
100%    5MB   1.7MB/s  00:03    

Downloading Program -- /home/zyrus/dev/scratch/project_1/design_1_wrapper/export/design_1_wrapper/sw/design_1_wrapper/boot/fsbl.elf
	section, .text: 0xfffc0000 - 0xfffced2b
	section, .note.gnu.build-id: 0xfffced2c - 0xfffced4f
	section, .init: 0xfffced80 - 0xfffcedb3
	section, .fini: 0xfffcedc0 - 0xfffcedf3
	section, .rodata: 0xfffcee00 - 0xfffcf2ef
	section, .sys_cfg_data: 0xfffcf300 - 0xfffcfb57
	section, .mmu_tbl0: 0xfffd0000 - 0xfffd000f
	section, .mmu_tbl1: 0xfffd1000 - 0xfffd2fff
	section, .mmu_tbl2: 0xfffd3000 - 0xfffd6fff
	section, .data: 0xfffd7000 - 0xfffd8217
	section, .sbss: 0xfffd8218 - 0xfffd823f
	section, .bss: 0xfffd8240 - 0xfffda57f
	section, .heap: 0xfffda580 - 0xfffda97f
	section, .stack: 0xfffda980 - 0xfffdc97f
	section, .dup_data: 0xfffdc980 - 0xfffddb97
	section, .handoff_params: 0xfffe9e00 - 0xfffe9e87
	section, .bitstream_buffer: 0xffff0040 - 0xfffffc3f

  0%    0MB   0.0MB/s  ??:?? ETA
100%    0MB   0.2MB/s  00:00    
Setting PC to Program Start Address 0xfffc0000
Successfully downloaded /home/zyrus/dev/scratch/project_1/design_1_wrapper/export/design_1_wrapper/sw/design_1_wrapper/boot/fsbl.elf
Info: Cortex-A53 #0 (target 9) Stopped at 0xffff0000 (Reset Catch)
_vector_table() at asm_vectors.S: 185
185: 	b	_boot
xsct% Info: Breakpoint 0 status:
   target 9: {Address: 0xfffcd04c Type: Hardware}
xsct% Info: Cortex-A53 #0 (target 9) Running
Info: Cortex-A53 #0 (target 9) Stopped at 0xffff0000 (Reset Catch)
xsct% 
initializing
  0%    0MB   0.0MB/s  ??:?? ETA
 18%    1MB   1.9MB/s  ??:?? ETA
 37%    1MB   1.9MB/s  ??:?? ETA
 51%    2MB   1.8MB/s  ??:?? ETA
 67%    3MB   1.8MB/s  ??:?? ETA
 84%    4MB   1.7MB/s  ??:?? ETA
100%    5MB   1.8MB/s  00:03    
Info: Cortex-A53 #0 (target 9) Stopped at 0xffff0000 (Reset Catch)
xsct% 
Downloading Program -- /home/zyrus/dev/scratch/project_1/design_1_wrapper/export/design_1_wrapper/sw/design_1_wrapper/boot/fsbl.elf
	section, .text: 0xfffc0000 - 0xfffced2b
	section, .note.gnu.build-id: 0xfffced2c - 0xfffced4f
	section, .init: 0xfffced80 - 0xfffcedb3
	section, .fini: 0xfffcedc0 - 0xfffcedf3
	section, .rodata: 0xfffcee00 - 0xfffcf2ef
	section, .sys_cfg_data: 0xfffcf300 - 0xfffcfb57
	section, .mmu_tbl0: 0xfffd0000 - 0xfffd000f
	section, .mmu_tbl1: 0xfffd1000 - 0xfffd2fff
	section, .mmu_tbl2: 0xfffd3000 - 0xfffd6fff
	section, .data: 0xfffd7000 - 0xfffd8217
	section, .sbss: 0xfffd8218 - 0xfffd823f
	section, .bss: 0xfffd8240 - 0xfffda57f
	section, .heap: 0xfffda580 - 0xfffda97f
	section, .stack: 0xfffda980 - 0xfffdc97f
	section, .dup_data: 0xfffdc980 - 0xfffddb97
	section, .handoff_params: 0xfffe9e00 - 0xfffe9e87
	section, .bitstream_buffer: 0xffff0040 - 0xfffffc3f

  0%    0MB   0.0MB/s  ??:?? ETA
100%    0MB   0.2MB/s  00:00    
Setting PC to Program Start Address 0xfffc0000
Successfully downloaded /home/zyrus/dev/scratch/project_1/design_1_wrapper/export/design_1_wrapper/sw/design_1_wrapper/boot/fsbl.elf
Info: Breakpoint 1 status:
   target 9: {Address: 0xfffcd04c Type: Hardware}
xsct% Info: Cortex-A53 #0 (target 9) Running
Info: Cortex-A53 #0 (target 9) Stopped at 0xfffcd04c (Breakpoint)
xsct% xsct% Info: Cortex-A53 #0 (target 9) Stopped at 0xfffc0000 (Hardware Breakpoint)
185: 	b	_boot
xsct% 
Downloading Program -- /home/zyrus/dev/scratch/project_1/ps_pl_comms_test/Debug/ps_pl_comms_test.elf
	section, .text: 0x00000000 - 0x00001503
	section, .init: 0x00001540 - 0x00001573
	section, .fini: 0x00001580 - 0x000015b3
	section, .rodata: 0x000015b8 - 0x00001657
	section, .rodata1: 0x00001658 - 0x0000167f
	section, .sdata2: 0x00001680 - 0x0000167f
	section, .sbss2: 0x00001680 - 0x0000167f
	section, .data: 0x00001680 - 0x00001e37
	section, .data1: 0x00001e38 - 0x00001e3f
	section, .note.gnu.build-id: 0x00001e40 - 0x00001e63
	section, .ctors: 0x00001e64 - 0x00001e7f
	section, .dtors: 0x00001e80 - 0x00001e7f
	section, .eh_frame: 0x00001e80 - 0x00001e83
	section, .mmu_tbl0: 0x00002000 - 0x0000200f
	section, .mmu_tbl1: 0x00003000 - 0x00004fff
	section, .mmu_tbl2: 0x00005000 - 0x00008fff
	section, .preinit_array: 0x00009000 - 0x00008fff
	section, .init_array: 0x00009000 - 0x00009007
	section, .fini_array: 0x00009008 - 0x00009047
	section, .sdata: 0x00009048 - 0x0000907f
	section, .sbss: 0x00009080 - 0x0000907f
	section, .tdata: 0x00009080 - 0x0000907f
	section, .tbss: 0x00009080 - 0x0000907f
	section, .bss: 0x00009080 - 0x000090bf
	section, .heap: 0x000090c0 - 0x0000b0bf
	section, .stack: 0x0000b0c0 - 0x0000e0bf

  0%    0MB   0.0MB/s  ??:?? ETA
100%    0MB   0.2MB/s  00:00    
Setting PC to Program Start Address 0x00000000
Successfully downloaded /home/zyrus/dev/scratch/project_1/ps_pl_comms_test/Debug/ps_pl_comms_test.elf
Info: Cortex-A53 #0 (target 9) Running
Info: Cortex-A53 #0 (target 9) Stopped at 0xd2c (Breakpoint)
main() at ../src/helloworld.c: 55
55:     init_platform();
xsct% Info: Cortex-A53 #0 (target 9) Stopped at 0xd30 (Step)
57:     Xil_Out32( XPAR_MYIP_0_S00_AXI_BASEADDR, 0x00000000 );
xsct% Info: Cortex-A53 #0 (target 9) Stopped at 0xd30 (Step)
57:     Xil_Out32( XPAR_MYIP_0_S00_AXI_BASEADDR, 0x00000000 );
xsct% Info: Cortex-A53 #0 (target 9) Running
xsct% Info: Cortex-A53 #0 (target 9) Stopped at 0x0 (Cannot continue stepping. Cortex-A53 #0: EDITR timeout)
xsct% 

 

Any guidance is sincerely appreciated.  Thanks!

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zigenz
Visitor
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Registered: ‎04-16-2019

OK - so it turns out that using Vivado 2019.1 with SDK worked perfectly!  Thanks for the suggestion Derek.  To be sure it was working end-to-end, I modified the AXI peripheral to flip a bit depending on the 32-bit register value and confirmed that it's doing what it should.

Regardless, what I was trying to achieve was literally the most basic possible workflow of PS/PL comms with an Ultrascale+; quite surprised that the latest version of the tooling doesn't (trivially) support this simple use-case to be honest!

View solution in original post

5 Replies
derekm_
Voyager
Voyager
508 Views
Registered: ‎01-16-2019

I don't use UltraScale. But I see that your platform project is out of date ("design1_wrapper"). You need to rebuild that, or clean it (or whatever works).

Some other things to try:

Does the Hello World application run with the Xil_In32() line commented out?

Have you tried using "Run as" instead of "Debug as" (with or without Xil_in32() commented out)?

Does your custom peripheral do anything i.e. can you simulate it in Vivado?

Have you tested this design in Vivado/SDK rather than Vitis? It is always worth having an earlier version of the tools installed on your system (I have 5 SDK versions and one Vitis!) so that you can verify things like this. Vitis is new. It is not perfect yet.

Not sure I will be able to help much more, but these are some things to try.

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zigenz
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Registered: ‎04-16-2019

Thanks Derek.

Apologies, the Explorer view screenshot was taken before I ran the first build.  The build system worked out the dependencies and built the platform project as part of the application (presumably it wouldn't have linked if it hadn't?).

Hello World runs fine and I can step through the code sans the Xil_Out32 line.

I'll try a few of the other things suggested and report back.  Appreciate the guidance.

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zigenz
Visitor
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Registered: ‎04-16-2019

OK - so it turns out that using Vivado 2019.1 with SDK worked perfectly!  Thanks for the suggestion Derek.  To be sure it was working end-to-end, I modified the AXI peripheral to flip a bit depending on the 32-bit register value and confirmed that it's doing what it should.

Regardless, what I was trying to achieve was literally the most basic possible workflow of PS/PL comms with an Ultrascale+; quite surprised that the latest version of the tooling doesn't (trivially) support this simple use-case to be honest!

View solution in original post

dgisselq
Scholar
Scholar
320 Views
Registered: ‎05-21-2015

@zigenz ,

While this wasn't your original problem, you should know that the AXI logic generated by the "Create and Package New IP" menu option has been broken for many years now.  I first noticed the bug in their AXI-lite slave logic with Vivado 2016, although I've seen bug reports dating back to 2014.  That logic has been only partially patched as of Vivado 2020.2.  I first noticed the bugs in their AXI (full) slave logic in 2018.3.  Since that time it has yet to be patched.

If you need an AXI slave template to start from, I might suggest this one instead.  Sure, use the "Create and Package New IP", but then rip the guts out of that broken core to build something that will actually work.

Dan

zigenz
Visitor
Visitor
298 Views
Registered: ‎04-16-2019

Thanks for the edifying snippet, Dan.  Appreciate the resource you shared also!

 

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