06-14-2013 12:19 PM
I created simple DMA with soft IP "AXI Direct Memory Access 6.02.a" The goal is to transfer streaming data to memory space which will use axi_s2mm.
Right now the software IP is in simple DMA mode. And the soft IP is in simulation process with Questa Sim. I can start one simple s2mm DMA by following the procedure in doc "PG021" Page 74. In the simulation, this DMA works well. I can see the "m_axi_s2mm_wdata" data streaming with the byte size setted.
Now the problem is that I cannot start another DMA. I tried to reset "S2MM_DMACR, 30h", "S2MM_DA, 48h" and "S2MM_LENGTH, 58h" and set again. The DMA cannot start again. The only weired thing I can notice is that "S2MM_DMASR, 34h" always read out "0000" after the first DMA. Before the first DMA, it is reading out "0001" which "Halted" bit is '1'. According to the datasheet, "S2MM_DMASR, 34h" bit 0 "Halted" should be asserted to '1' if set DMACR.RS to '0'. But I can see "Halted" is always '0' no matter what I do.
I am just wondering whether is anything I did wrong.
06-14-2013 01:38 PM
Thank you very much for your suggestions. I did notice that I didn't drive these two signals undrived.
I will do the signal driving. If it works, I will wrap this question.
06-17-2013 11:12 AM
I still have trouble on this DMA simulation. I think it is not the problem tkeep/tlast. My initial problem is that the m_axi_s2mm_bvalid is not drive.
Without driving signal m_axi_s2mm_bvalid, the DMA thought it is not done and then it will keep running. This cauases I cannot start a new DMA.
After this signal is corrected, I start to get the error message in S2MM_DMASR.DMAIntErr (0-> 1). But here problem is that this bit is only for Scatter/Gather mode, not for simpel DMA mode. I double checked with the C_INCLUDE_SG which is "0". In the datasheet, it notes "This bit is not used and is fixed at 0 when AXI DMA is configured for simple DMA mode".
Whether it is bug on the IP? According to the datasheet, S2MM_DMASR.DMAIntErr couldn't be "1" with simple DMA mode I set.
06-17-2013 11:25 AM
06-17-2013 12:54 PM
Thank you for the quick reply.
After I posted the last message, I did add one more step before each DMA set. The step is soft reset the AXI DMA for around 8 clock cycles (S2MM_DMACR.Reset = '1'). With this step, I saw all the DMA are working correctly. And the data from the S2MM memory map interface side are the one I expected. I am kindly confident that the data correctly transferred?
My testcase is a little complicated. If necessary, I would like to create a simple one for you try. But before it, I would like to know how to ignore the error and see whether it is working or not. Software reset is not a preferred method I would like to use. I think you must have a better way to do that.
09-09-2013 04:55 PM
Don't know if you came right, but I was having a similar problem and got it working.
I found that driving TLAST high during the entire transfer solves the issue regarding the S2MM_DMASR.DMAIntErr error. (By default TLAST of the DMA stream input is driven low in XPS causing this error, if it is not connected to a TLAST from the peripheral)
The S2MM_DMASR.DMAIntErr bit will not be set on MM2S, but it can be set in S2MM:
"When, C_INCLUDE_SG=0, this error is flagged if there is any error during Memory write or if the incoming packet is bigger than what is specified in the DMA length register."
If you assert TLAST for the entire transfer, you don't get the error and don't need to reset the dma after each transfer...
If TLAST is not asserted, the DMA sees the incoming stream as an incomplete packet, and expects more data, causing the error.
09-10-2013 09:07 AM
Thank you for the answer. You are right, the TLAST signal need to be asserted at the last data.
But seems assert TLAST for the entire transfer doesn't work. It will treat the data with the first TLAST asserted as the last data and didn't transfer the left data. In my test case, I have to assert the exact TLAST signal to transfer the data I specified. Then, the DMA length can be either equal to or bigger than the length of data transferred.
From the S2MM_DMASR.Halted, it seems that the DMA is still working. But I can start another DMA without reset the DMA engine.
That's what i found with my test.
Thanks again for the suggestion. It really helpful.
09-11-2013 04:11 PM
Yes you're right. TLAST must only be asserted on the last sample, otherwise it does not transfer all the data.
03-08-2015 10:37 PM
Could you please tell me that the 8 clock cycle duration of reset given to AXI DMA is a calculated one or a random guess.
I am facing with the similar incident and I am forcing the soft reset on my DMA for one clock cycle and this is not resetting my DMA. The value of S2MM_DMACR is fixed and is not changing although I am able to write to other two regesters S2MM_DESTINATION and S2MM_LENGTH.