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vapham
Contributor
Contributor
366 Views
Registered: ‎06-02-2019

Two independent AXI SPI Masters

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Hello everyone,

My ideal is using 2 SPI AXI as master in the same design.

At the same time, these Masters could send different data to two devices which connect to FPGA board.

This is my design:

block_design_2_spis.thumb.png.70bb959d8f2c3eb2f7d7442689d172f7.png

I tried to test one by one SPI and it works well,

But It did not work with two SPIs. Is there any conflict in SPI bus? Anyone could point out the issue pls?

Thank you

 

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venui
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Registered: ‎04-09-2019

Hi @vapham 

If you are using bare-metal application its not possible to transfer data parallelly because the bare-metal source code executes serially, but in OS environment its possible to transfer data parallelly using thread mechanism.

So I think its not possible with bare-metal environment.

Regards 

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dpaul24
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Registered: ‎08-07-2014

@vapham ,

Is the problem in the master side or slave side?

Also note that the Zynq can address only 1 SPI master at a time.

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vapham
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Registered: ‎06-02-2019

@dpaul24 

Thank you for your quick reply,

How about if I use Zynq Ultrascale? The problem is from SPI Master side (I can only send the value by using one Master SPI at one time - but my expect is two master SPIs at one time)

Regards

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venui
Moderator
Moderator
160 Views
Registered: ‎04-09-2019

Hi @vapham 

If you are using bare-metal application its not possible to transfer data parallelly because the bare-metal source code executes serially, but in OS environment its possible to transfer data parallelly using thread mechanism.

So I think its not possible with bare-metal environment.

Regards 

View solution in original post

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