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Observer
Observer
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Registered: ‎08-14-2017

Two questions about PL and PS VCCO power rail of zynq ultrascale+ MPSOC

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Hello,


I have two questions about PL and PS VCCO power rail of zynq ultrascale+ MPSOC:


(1) Can the PL and PS VCCO_[bank] of zynq ultrascale+ MPSOC share a common power rail in a board? 

 

(2) Can the PL / PS VCCO_[bank] share the power rail with other chips in a board?

 

Thanks!

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Moderator
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Registered: ‎07-23-2015

Re: Two questions about PL and PS VCCO power rail of zynq ultrascale+ MPSOC

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@luckzzylb Please follow UG583. XTP427 is going to have this (VCCO_PSIO) fixed in the next revision (Already aware  of this issue)

 

As mentioned above, just make sure the voltage rails clubbed meet the data sheet requirements for voltage and tolerance.

- Giri
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Scholar
Scholar
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Registered: ‎02-27-2008

Re: Two questions about PL and PS VCCO power rail of zynq ultrascale+ MPSOC

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If they are the same voltage, yes, and yes.

 

Please check you stay within the recommended ranges for all supplies, at all times.

 

In some safety critical applications, sharing supplies is a common failure mechanism, and is not done.  Otherwise, if anything requires a particular voltage, and the noise and variations are within specifications, a common supply rail is just fine.

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Observer
Observer
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Registered: ‎08-14-2017

Re: Two questions about PL and PS VCCO power rail of zynq ultrascale+ MPSOC

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@austin, thanks for your help

According to ug583 chapter4Power Supply Consolidation Solutions for Zynq UltraScale+ MPSoCs:Figure 4-1.png

The dashed lines in figure 4-1 means the VCCO_PSIO and VCCO can share a common power rail. So, in our board, we have a design as follows:

our design.png

However, in the xtp427  "ultrascale plus schematic review checklist" , it says “the VCCO_PSIO cannot be combined with any other rails”:

Checklist.png

Now , we are confused.  Which one is correct?  The ug583 or xtp427?

 

 

 

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Scholar
Scholar
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Registered: ‎02-27-2008

Re: Two questions about PL and PS VCCO power rail of zynq ultrascale+ MPSOC

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Good catch!


I will check with the designers.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Observer
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Re: Two questions about PL and PS VCCO power rail of zynq ultrascale+ MPSOC

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@austin, so is there the mistake in xtp427?

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Moderator
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Registered: ‎07-23-2015

Re: Two questions about PL and PS VCCO power rail of zynq ultrascale+ MPSOC

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@luckzzylb Please follow UG583. XTP427 is going to have this (VCCO_PSIO) fixed in the next revision (Already aware  of this issue)

 

As mentioned above, just make sure the voltage rails clubbed meet the data sheet requirements for voltage and tolerance.

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
-----------------------------------------------------------------------------------------------------------------------

View solution in original post

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