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Explorer
Explorer
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Registered: ‎03-26-2010

UART 16550 is BROKEN in Microblaze/2018.2 designs

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This is rather ridiculous, but is still a problem. Using Vivado 2018.2, creating a block diagram with Microblaze and the UART 16550 2.0

Project fails in Place with the following message:

[Place 30-1114] Floating OSERDES NO_EXTERNAL_XIN.OSERDESE3_ODDR_GEN.BAUD_FF is not placed and is not a part of any Shape. It won't be placed by the IO Placer.

This is completely not OK.

Only UART pins that are brought out are the Tx and Rx.

On 2017.4 this implements fine, and the placer trims away the un-used OSERDES. The OSERDES is inside the UART core and was generated by Xilinx IP.

 

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Explorer
Explorer
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Registered: ‎03-26-2010

The workaround is to issue a place constraint for the OSERDES, which lets the tool bypass the error and then still trim it from the design later.

 

Still an idiotic thing to have to do, but at least I can move on with 2018.2. The 2018.3 version does not have this problem either.

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Highlighted
Explorer
Explorer
442 Views
Registered: ‎03-26-2010

The workaround is to issue a place constraint for the OSERDES, which lets the tool bypass the error and then still trim it from the design later.

 

Still an idiotic thing to have to do, but at least I can move on with 2018.2. The 2018.3 version does not have this problem either.

View solution in original post

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