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reza_ameli
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Registered: ‎03-05-2021

ULPI timing failure

I'm using the AXI Universal Serial Bus (USB) 2.0 Device v5.0 and have a timing closure problem.

The ULPI ports are:

input wire ULPI_CLK,
inout wire [7:0] ULPI_DATA,
input wire ULPI_DIR,
input wire ULPI_NEXT,
output wire ULPI_RST,
output wire ULPI_STOP,

And my constraints are (according to PG137 

create_clock -name clk_ulpi -period 16.667 [get_ports {ULPI_CLK}]
set ulpi_input {ULPI_DIR ULPI_NEXT ULPI_DATA[0] ULPI_DATA[1] ULPI_DATA[2] ULPI_DATA[3] ULPI_DATA[4] ULPI_DATA[5] ULPI_DATA[6] ULPI_DATA[7]}
set ulpi_output {ULPI_STOP ULPI_RST}
set_input_delay -max 4.5 -clock clk_ulpi [get_ports $ulpi_input]
set_output_delay -max 7 -clock clk_ulpi [get_ports $ulpi_output]
set_max_delay 24 -from [get_ports ULPI_DIR] -to [get_ports ULPI_DATA[*]] -datapath_only


The frequency of the s_axi_aclk of the IP is 100 MHz which should be ok according to page 49 of PG137 .
But I am getting a WNS of -14.954 ns on the ULPI_RST port.
Any help would be appreciated with this.

Thank you!

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