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Xil_printf
Visitor
Visitor
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Registered: ‎02-25-2021

USB3320 PHY USB Mass storage example works intermittently

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Hi all,

I have a custom Ultrascale board with the USB3320 PHY. I am running the mass storage driver Bare metal example. When it works, I am able to connect and disconnect to my host PC as many time as I want without issues, However it works intermittently as I power cycle the board or reprogram it. It seems to work more often with quick power cycles. Can anyone please help? The reset pin is connected to an MIO. I am resetting the PHY through this MIO in software.  I am aware of Zync MIOs possibly confusing the PHY and changed my fsbl to configure the control MIOs after the DATA MIOs as metioned in this post https://forums.xilinx.com/t5/Processor-System-Design-and-AXI/ULPI-Initialization-timeout-on-Zynq-based-board/m-p/936241

The problem didn't change. Here is my schematic:

 

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usb_schematic.png
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Xil_printf
Visitor
Visitor
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Registered: ‎02-25-2021

Got it to work. Make sure that the Pullups on the MIO Lines are disabled in Vivado. That solved my problem. However, I only see it as a USB 2.0 device. Do I need to do anything in the driver code to make it work for the USB3.0? I have GT Lane0 and the right clock speed configured in vivado. Wondering if there is anything in the driver code I need to add or configure.

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jadhavs
Xilinx Employee
Xilinx Employee
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Registered: ‎01-21-2008

Hi @Xil_printf ,

Baeremetal USB driver based example is kind of a while loop for getting this USB MSD(Mass Storage Device) to work. Probably there could be the race condition where the ULPI PHY is not ready and the application might be executed before the enumeration of the USB from the HOST side. Try to add some delay in your example design and see if that works for you. This is to see if there is any delay or timing cause for setting up the USB enumeration at the HOST side. Probably you need to use embedded Linux drivers for such kind of application going forward.  

Xil_printf
Visitor
Visitor
341 Views
Registered: ‎02-25-2021

Got it to work. Make sure that the Pullups on the MIO Lines are disabled in Vivado. That solved my problem. However, I only see it as a USB 2.0 device. Do I need to do anything in the driver code to make it work for the USB3.0? I have GT Lane0 and the right clock speed configured in vivado. Wondering if there is anything in the driver code I need to add or configure.

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drjohnsmith
Teacher
Teacher
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Registered: ‎07-09-2009

You only have two USB lines to the USB connector,

   thus you can not be USB 3, that requires at least 6 connections,

You only have two USB lines as the USB3320 is a USB 2 chip,

 

   

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Xil_printf
Visitor
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Registered: ‎02-25-2021

@drjohnsmith  @jadhavs  I do have the lines for USB 3.0 connected (not shown in above diagram).  I'm wondering if there is anything on the driver side I need to change.

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drjohnsmith
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Teacher
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Registered: ‎07-09-2009

Not from that chip you don't,

 

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Xil_printf
Visitor
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Registered: ‎02-25-2021

@drjohnsmith Not from that USB3320 Chip! Like you said that's a USB 2.0 PHY. I have the TX,RX, differentials connected from the FPGA to the USB port. Did you get the usbpsu driver to work with USB3.0?

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drjohnsmith
Teacher
Teacher
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Registered: ‎07-09-2009

not had it working with a USB 2 chip and a separate USB3 solution

 

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