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shepsoft
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Registered: ‎10-12-2020

Ultrascale linear addressing QSPI with NVRAM

Hi all,

I'm doing a feasibility study on new build and trying to pin down one point (right now anyway... I'll have more!)

So this is essentially the same question as posted here:

https://forums.xilinx.com/t5/Processor-System-Design-and-AXI/QSPI-nvRAM/m-p/856661#M39530

Although it conflicts with this answer:

https://forums.xilinx.com/t5/Processor-System-Design-and-AXI/Linear-QSPI-addres-with-ZC702-board/td-p/685610

Where the answerer is very insistent you can't write in linear mode, although that is an old post, so things may have changed.

But then in this wiki:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842262/Zynq+QSPI+Driver

Under 'Linear addressing mode' bullet point is says: 'Memory reads and writes are interpreted by the controller'

So, which is it? Anyone used it in this way in anger?

As mentioned in the first post, all the documentation is geared towards QSPI being use for flash (heavens it should be used for anything else!), however I want to use it as NV storage for the RP, and things would be so much easier if I could both read from and write to the device directly via address accesses, as opposed to shadowing in RAM etc.

Specifically I would like to use it with MRAM:

https://www.everspin.com/family/mr10q010?npath=259

It appears the same OP codes are supported as flash (0x03 for read, 0x02 for write and so on), although the ultrascale ref manual read/program command example have 4 address bytes, or 3 and a dummy, and the MRAM has 3 address bytes. Also the write command uses the exponent for bytes to write.

 

Basically, I just can't tell if it'd work or not!

Thanks.

 

 

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