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bumblebee_man
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Registered: ‎08-01-2016

Unable to perform partial readback of PL using PCAP

Hello, 

I'm currently working on a project that requires partial readback of the programmable logic on my Zynq device (by PS using PCAP). I created a reconfigurable partition that should be readback without interfering the remaining parts of the PL.
Unfortunately, I haven't found any documentation on such a procedure. Hence, I tried to adapt the provided xdevcfg "polled write example" to read the PL partially. To some extent it is working properly, since it successfully reads back entire PL bitstreams. But if I set the FAR to the starting address of my reconfigurable partition (found in the partial bitstream file) and the "amount of bytes to be read" to the size of my reconfigurable partition, PCAP returns data with all bytes set to zero (not a single bit is equal to "1").

The SDK code (file attached) I use is based on the example mentioned above and the readback command sequence is based on UG470 page 127.

Do I have to adjust the command sequence for "partial readback"?

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balkris
Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008

Configure the PL before attempting PL Readback operations through the PCAP

check this ARs

http://www.xilinx.com/support/answers/47578.html
Thanks and Regards
Balkrishan
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bumblebee_man
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Registered: ‎08-01-2016

Thanks Balkrishan,

 

I configured the PL using Vivado Hardware Manager prior executing the readback code. But I do not get a proper partial readback result. Reading back the entire configuration works just fine. My problem is performing reads partially.

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bumblebee_man
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Registered: ‎08-01-2016

I fixed the problem of reading just zeros during partial readback by disabling the cache [i.e. by adding Xil_DCacheDisable(); and
Xil_ICacheDisable(); to my code].

 

Unfortunately, I'm now faced with another problem:

My Zynq will be shut down during the readback procedure, but it does not (re)start after receiving the start command in the second part of the command sequence. It stays shut down and the DevC DMA Command Queue never get empty again. I.e. polling the XDCFG_STATUS_DMA_CMD_Q_E bit creates an infinite loop in my code. 

My code is still based on the DevC example code and the readback command sequence found in UG470. 

PS: My setup remains unchanged. I'm using a Zedboard, which is configured using Vivado's Hardware Manager and read back using the attached code. The readback seems to work fine now, but the PL does not restart after receiving the START command.

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Registered: ‎04-20-2019

Hi,

I  am trying to perform PL readback through PCAP on ZED Board. I have already configured the PL using Vivado Hardware Manager. But when i load readback code my bit file seems erased and my FPGA shuts down. I have passes the commands mention in UG 470 to my readback transfer function.

Is there any DevC example for reading back the file(either full bit stream or partial) from PL.

Thanks

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