06-24-2014 05:35 PM
I'm using a reference design that includes an Analog to Digital Converter (ADC) connected to the FMC connector, a Microblaze, a Direct Memory Access (DMA) peripheral and DDR3 Ram. This is my first time using a design that contains a DMA peripheral. I've been reading the documentation on it and have read through tutorials on it, but I still feel like I'm missing some fundamentally basic knowledge on why I should use it. I'm hoping someone can help me understand this better.
As I understand the design right now, the DMA is used to take streaming data from the ADC and map it to memory, what is labeled as a Slave to Memory Mapped (S2MM) transfer. This is why a DMA is required. The standard AXI Interconnect peripheral cannot handle streaming data. Am I correct so far? Is the statement that anytime I use AXI-Streaming I will need to include a DMA correct?
How does the DMA determine a destination address for a stream? Is this built in somewhere? If the stream ends, how does the DMA know?
As the DMA is filling up some block of memory, is there protection against overflowing? Will I be told if it filled the RAM up faster then I could read the data? Can I set boundaries on the base and high addresses for the DMA block to fill?
Thanks for helping me to understand this better. It's very new to me.
06-24-2014 10:44 PM
Each has a specific use case .
1) AXI CDMA - Memory-mapped to memory-mapped transfers (i.e. if your BRAM is already hanging off the AXI interconnect, this will probably be the best bet)
2) AXI Datamover - AXI Stream to AXI Memory Mapped conversion, but you have lower level control of commands (most likely don't need to use this unless you need some sort of custom DMA operations or something)
3) AXI DMA - AXI Stream to AXI memory-mapped transfers (i.e. if your BRAM is NOT hanging off the AXI interconnect already, this might be easiest to interface to)
4) AXI VDMA - Similar to AXI DMA, but it does 2D transfers and has some other video-specific features (probably not what you want, unless you're doing video/imaging)
If you are not going for SCatter-gather mode, basically the register direct mode, then this mode transfers are commanded by setting a Source Address (for MM2S) or Destination Address (For S2MM) and then specifying a
byte count in a length register.
There are specific errors thats thrown for DMA ro exit any specific scenarios. Please check the product guide for detailed information.Any detected error results in the AXI DMA gracefully halting. When an error is detected, the
errored channel DMACR.RS bit is set to 0.
06-25-2014 09:14 AM
06-25-2014 04:34 PM
There are a number of reasons why you would use a DMA engine. As the name suggests, the ultimate goal is to move data around in some memory-style format.
The most common use for generic 'DMA' is to offload a processor from having to do individual transfers from one place to another. As you can imagine, this is very wasteful and slow/inefficient (since CPU only does single-word accesses).
That said, there are other good reasons for using different types of DMAs. As you have noticed, one such application is to move streaming data to memory. In your ADC example, your incoming data has no notion of addressing. It's just a serial stream of samples. How do you get that into external DDR so you can buffer it or do something else with it? You need to packetize that data, assign addresses, and formulate commands that adhere to the bus protocol you desire (i.e. AXI). This is no trivial task. Thus, AXI DMA core.
How does the DMA determine a destination address for a stream? Is this built in somewhere? If the stream ends, how does the DMA know? As the DMA is filling up some block of memory, is there protection against overflowing? Will I be told if it filled the RAM up faster then I could read the data? Can I set boundaries on the base and high addresses for the DMA block to fill?
All very good questions. I'll try to answer them:
1) How does the DMA know the destination address? Someone must tell it the destination address. That is typically a processor, but could be some little custom piece of hardware that speaks AXI Lite
2) If the stream ends, how does the DMA know? What do you mean by 'if the stream ends' ? In general, you would tell the DMA the destination address and the number of bytes to transfer. The DMA increments addresses until bytes_to_transfer number of bytes are complete. Then it will fire an interrupt and wait for you to tell it what to do again.
3) Overflow? Well, as I mentioned, you typically (for our DMAs, anyway) specify the number of bytes to transfer, so there's not really any concern here. Presumably, you have been careful to select your address and num_bytes appropriately. However, there is a concept of 'Cyclic' mode where the DMA sort of implements a circular buffer and streams data continuously. In such cases, once the end of the buffer is reached, the pointer goes back to the start and you start overwriting the oldest samples. That's the software's job to make sure it does something with the data before it gets overwritten. There are interrupts to help you keep track of such things. Make sure to read the AXI DMA PG and study examples. I've posted several example designs if you search my old posts.
06-25-2014 05:52 PM
06-26-2014 08:27 AM
Well, it depends :).
If we are still talking about your custom peripheral being an ADC (and assuming a reasonably 'fast' data rate), I am going to say yes, you should use a DMA. It will be the most efficient and will allow microblaze to do other things.
Now if your peripheral is something else where data is really slow and not consistent or something like that, then you have other options. For example, you could use a GPIO and periodically read it (from microblaze) as necessary to grab incoming words. You could also use the AXI Stream ports on microblaze along with the special push/pop instructions that access those ports.
You really do have a lot of options and the 'best' one depends on a number of factors.
06-26-2014 02:21 PM
06-26-2014 02:25 PM
04-13-2016 08:26 AM
04-13-2016 10:16 AM
Bytes to Transfer. This register field is used for Simple DMA transfers and indicates the desired number of bytes to DMA from the Source Address to the Destination Address. A maximum of 8,388,607 bytes of data can be specified by this field for the associated transfer. Writing to the BTT register also initiates the Simple DMA transfer.