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10,933 Views
Registered: ‎01-07-2014

Understanding the DMA Peripheral

Hello,

 

I'm using a reference design that includes an Analog to Digital Converter (ADC) connected to the FMC connector, a Microblaze, a Direct Memory Access (DMA) peripheral and DDR3 Ram. This is my first time using a design that contains a DMA peripheral. I've been reading the documentation on it and have read through tutorials on it, but I still feel like I'm missing some fundamentally basic knowledge on why I should use it. I'm hoping someone can help me understand this better.

 

As I understand the design right now, the DMA is used to take streaming data from the ADC and map it to memory, what is labeled as a Slave to Memory Mapped (S2MM) transfer. This is why a DMA is required. The standard AXI Interconnect peripheral cannot handle streaming data. Am I correct so far? Is the statement that anytime I use AXI-Streaming I will need to include a DMA correct?

 

How does the DMA determine a destination address for a stream? Is this built in somewhere? If the stream ends, how does the DMA know?

 

As the DMA is filling up some block of memory, is there protection against overflowing? Will I be told if it filled the RAM up faster then I could read the data? Can I set boundaries on the base and high addresses for the DMA block to fill?

 

Thanks for helping me to understand this better. It's very new to me.

 

v/r,

Rich

 

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12 Replies
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Xilinx Employee
Xilinx Employee
10,925 Views
Registered: ‎06-14-2012

Re: Understanding the DMA Peripheral

Hi Rich

Each has a specific use case .

1) AXI CDMA - Memory-mapped to memory-mapped transfers (i.e. if your BRAM is already hanging off the AXI interconnect, this will probably be the best bet)

2) AXI Datamover - AXI Stream to AXI Memory Mapped conversion, but you have lower level control of commands (most likely don't need to use this unless you need some sort of custom DMA operations or something)

3) AXI DMA - AXI Stream to AXI memory-mapped transfers (i.e. if your BRAM is NOT hanging off the AXI interconnect already, this might be easiest to interface to)

4) AXI VDMA - Similar to AXI DMA, but it does 2D transfers and has some other video-specific features (probably not what you want, unless you're doing video/imaging)

 

If you are not going for SCatter-gather mode, basically the register direct mode, then  this mode transfers are commanded by setting a Source Address (for MM2S) or Destination Address (For S2MM) and then specifying a 

byte count in a length register.

 There are specific errors thats thrown for DMA ro exit any specific scenarios. Please check the product guide for detailed information.Any detected error results in the AXI DMA gracefully halting. When an error is detected, the 

errored channel DMACR.RS bit is set to 0. 

http://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf

Regards

Sikta

 

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10,905 Views
Registered: ‎01-07-2014

Re: Understanding the DMA Peripheral

Sikta,

I think I'm more confused now then before. I did not know CDMA, Datamover and VDMA existed.

Why does CDMA exist. Memory mapped to Memory mapped sounds like what the AXI Interconnect itself is supposed to be doing. What am I missing?

Let me pose the question like this. If we did not include any DMA on an AXI-Lite bus, what would happen? In my mind, you would be able to do memory mapped to memory mapped transfers like you'd expect. What I'm not sure of now, is if the CPU needs to be added to the mix to make decisions. I need some guidance on this level of detail.

Thanks,
Rich
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10,900 Views
Registered: ‎01-07-2014

Re: Understanding the DMA Peripheral

Really interested in some explanation by a skilled designer here.
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Xilinx Employee
Xilinx Employee
10,895 Views
Registered: ‎08-02-2011

Re: Understanding the DMA Peripheral

Hi Rich,

 

There are a number of reasons why you would use a DMA engine. As the name suggests, the ultimate goal is to move data around in some memory-style format.

 

The most common use for generic 'DMA' is to offload a processor from having to do individual transfers from one place to another. As you can imagine, this is very wasteful and slow/inefficient (since CPU only does single-word accesses).

 

That said, there are other good reasons for using different types of DMAs. As you have noticed, one such application is to move streaming data to memory. In your ADC example, your incoming data has no notion of addressing. It's just a serial stream of samples. How do you get that into external DDR so you can buffer it or do something else with it? You need to packetize that data, assign addresses, and formulate commands that adhere to the bus protocol you desire (i.e. AXI). This is no trivial task. Thus, AXI DMA core.

 

How does the DMA determine a destination address for a stream? Is this built in somewhere? If the stream ends, how does the DMA know?
 
As the DMA is filling up some block of memory, is there protection against overflowing? Will I be told if it filled the RAM up faster then I could read the data? Can I set boundaries on the base and high addresses for the DMA block to fill?

 

All very good questions. I'll try to answer them:

1) How does the DMA know the destination address? Someone must tell it the destination address. That is typically a processor, but could be some little custom piece of hardware that speaks AXI Lite

2) If the stream ends, how does the DMA know? What do you mean by 'if the stream ends' ? In general, you would tell the DMA the destination address and the number of bytes to transfer. The DMA increments addresses until bytes_to_transfer number of bytes are complete. Then it will fire an interrupt and wait for you to tell it what to do again.

3) Overflow? Well, as I mentioned, you typically (for our DMAs, anyway) specify the number of bytes to transfer, so there's not really any concern here. Presumably, you have been careful to select your address and num_bytes appropriately. However, there is a concept of 'Cyclic' mode where the DMA sort of implements a circular buffer and streams data continuously. In such cases, once the end of the buffer is reached, the pointer goes back to the start and you start overwriting the oldest samples. That's the software's job to make sure it does something with the data before it gets overwritten. There are interrupts to help you keep track of such things. Make sure to read the AXI DMA PG and study examples. I've posted several example designs if you search my old posts.

www.xilinx.com
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10,890 Views
Registered: ‎01-07-2014

Re: Understanding the DMA Peripheral

Thanks bwiec. I will search your old posts.

Can you answer me this question: If I have an AXI-Lite bus with DDR3 memory, a MicroBlaze and a Custom peripheral attached to it and nothing else, do I require a DMA? If not, where are addressing decisions being made in this scenario. Who is looking at the destination address and routing it there? Is it the AXI Interconnect peripheral?

Thanks again,
Rich
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Xilinx Employee
Xilinx Employee
10,883 Views
Registered: ‎08-02-2011

Re: Understanding the DMA Peripheral

Hi Rich,

 

Well, it depends :).

 

If we are still talking about your custom peripheral being an ADC (and assuming a reasonably 'fast' data rate), I am going to say yes, you should use a DMA. It will be the most efficient and will allow microblaze to do other things.

 

Now if your peripheral is something else where data is really slow and not consistent or something like that, then you have other options. For example, you could use a GPIO and periodically read it (from microblaze) as necessary to grab incoming words. You could also use the AXI Stream ports on microblaze along with the special push/pop instructions that access those ports.

 

You really do have a lot of options and the 'best' one depends on a number of factors.

www.xilinx.com
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10,877 Views
Registered: ‎01-07-2014

Re: Understanding the DMA Peripheral

I still don't understand bwiec. Forget about the ADC in my previous example. I'm most interested in understanding the basics of addressing with the AXI bus now I think.

If there is no DMA, and I send a Xil_Out32(addrr, value) command from the microblaze which should send data to memory, what device makes sure the data is routed to the correct address. Is that the AXI Interconnects responsibility?
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Xilinx Employee
Xilinx Employee
10,875 Views
Registered: ‎08-02-2011

Re: Understanding the DMA Peripheral

Hi Rich,

Yes, that is correct that the interconnect routes the data from microblaze to the correct peripheral based on the address for that transaction.
www.xilinx.com
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Contributor
Contributor
5,712 Views
Registered: ‎02-18-2014

Re: Understanding the DMA Peripheral

Hi @bwiec, richard.bell1@navy.mil, @siktap,

 

I have a little question about the microblaze axi4 cdma, I didn't saw it anywhere (may be it was...), but how much byte to transfer the CDMA support ?

 

thanks in advance for your repplies,

 

Regard,

 

J.

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Xilinx Employee
Xilinx Employee
3,289 Views
Registered: ‎08-02-2011

Re: Understanding the DMA Peripheral

Hello,

 

From PG034:

 

Bytes to Transfer. This register field is used for Simple
DMA transfers and indicates the desired number of bytes
to DMA from the Source Address to the Destination
Address. A maximum of 8,388,607 bytes of data can be
specified by this field for the associated transfer.
Writing to the BTT register also initiates the Simple DMA
transfer.
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Contributor
Contributor
3,270 Views
Registered: ‎02-18-2014

Re: Understanding the DMA Peripheral

Hi @bwiec,

 

I appologize for this loss of time... Thank you for your repply.

 

Best regards,

 

J.

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Xilinx Employee
Xilinx Employee
3,262 Views
Registered: ‎08-02-2011

Re: Understanding the DMA Peripheral

Oh no need to apologize. We're here to help!

Have a great day.
www.xilinx.com
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