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Observer
Observer
4,681 Views
Registered: ‎12-12-2007

Using 1GB RAM for ML510

Hi,

 

I am working on ML510 with EDK 10.1.3 and there is two  Wintec 1GB RAM on the board. In the EDK there is no support for this model of RAM. How can I import this model in EDK in order to use it?

 

Thanks in advance,

Nikos 

 

 

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Historian
Historian
4,670 Views
Registered: ‎02-25-2008

 


@hulkakos wrote:

Hi,

 

I am working on ML510 with EDK 10.1.3 and there is two  Wintec 1GB RAM on the board. In the EDK there is no support for this model of RAM. How can I import this model in EDK in order to use it?

 

Thanks in advance,

Nikos 

 

 


Write your own memory controller.

 

----------------------------Yes, I do this for a living.
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Participant
Participant
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Registered: ‎05-02-2009

 


@bassman59 wrote:

 

Write your own memory controller.

 


  quite uninspired...

 

 

Of course there are ways to include other DIMMs than those mentioned in the MPMC drop-down list.

 

The dropdown list is generated with the help of the file mpmc_memory_database.cvs located at <your_path>/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v6_01_a/data

 

In this file copy and paste line

DIMM,DDR2,512MB,x64,Wintec,1,64,WD2RE512X809-667D,64,8,2,14,10,45000,70000000,60000,15000,,15000,15000,2,7500,105000,7800000,0,2,7500,7500,400,3,533,4,667,5,0,0,1,1,1,1,1

and change the fields to
DIMM,DDR2,1GB,x64,Wintec,1,64,WD2RE01GX809-667D,64,8,3,14,10,45000,70000000,60000,15000,,15000,15000,2,7500,105000,7800000,0,2,7500,7500,400,3,533,4,667,5,0,0,1,1,1,1,1

 

Afaik the only difference between the 512 MB and 1 GB DIMMs is the densities of the components - the timings are identical. To address the doubled RAM Size a third bank address signal (BA2) is used.

After restarting the XPS the new DIMM is available in the MPMC dropdown list.

 

If you use the powerpc440 memory controller rather than an mpmc, just modify the bank address width to "3" in the GUI.

In the PPC440 GUI change the value of "Mask Used to Determine a Bank Confict" from 0x0180000 to 0x03800000.

 

After those settings are applied, you also have to adjust the ucf file accordingly.

For existing projects add the line

Net fpga_0_DDR2_SDRAM_DIMM0_DDR2_BA_pin<2> LOC=K39  |  IOSTANDARD = SSTL18_II;  # for DIMM0

to your ucf.

For new projects you can also change the ML510 board definition file Xilinx_ML510_v###.xbd located at <your_path>/EDK/board/Xilinx/boards/Milinx_ML510/data which is read when a new project on the ML510 is created.

 

Modify the following lines for both DIMMs:

 

PARAMETER C_MEM_PARTNO="WD2RE01GX809-667D", IO_IS=C_MEM_PARTNO

PARAMETER C_HIGHADDR = 0x3fffffff, IO_IS = C_HIGHADDR

PARAMETER C_MEM_BANKADDR_WIDTH = 3, IO_IS = C_MEM_BANKADDR_WIDTH

PARAMETER C_PPC440MC_BANK_CONFLICT_MASK = 0x03800000, IO_IS = C_PPC440MC_BANK_CONFLICT_MASK

 

uncomment the following lines:

PORT DDR_BankAddr_2 = dimm0_ddr2_ddr_bankaddr_2, IO_IS = ddr2_BankAddr[2]

PORT DDR_BankAddr_2 = dimm1_ddr2_ddr_bankaddr_2, IO_IS = ddr2_BankAddr[2]

PORT dimm0_DDR2_DDR_BANKADDR0 =dimm0_ddr2_ddr_bankaddr_2, UCF_NET_STRING=("LOC=K39", "IOSTANDARD = SSTL18_II")

PORT dimm1_DDR2_DDR_BANKADDR0 = dimm1_ddr2_ddr_bankaddr_2, UCF_NET_STRING=("LOC=AH35", "IOSTANDARD = SSTL18_II")

 

It would be nice if a Xilinx guy could verify this description, but it seems to work with my ML510/ISE12.2 combination.

 

Regards

marco

 

 

 

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Instructor
Instructor
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Registered: ‎07-21-2009

You may want to check on this, but I suspect the 1GB module has 3-bit bank address  vs. 2-bit bank address for the 512MB module.  Depending on how the RAS/CAS addresses and bank address are ordered, this may affect your design.

 

1Gbit DRAMs have 3-bit bank address, 512Mbit and smaller DRAMs have 2-bit bank address.

 

- Bob Elkind

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Adventurer
Adventurer
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Registered: ‎05-11-2010


@bassman59 wrote:

 

Write your own memory controller.


I don't think that was very helpful.


Xilinx's Answer Record #35678 suggests setting the BankAddress[2] pin to 0, but I don't think that's a good solution since it wastes half of the RAM (which is still better than wasting all of it).

I have tried schneemann79's solution on Xilinx 14.1 and it seems to work fine.  I made a patch for mpmc_memory_database.csv and Xilinx_ML510_v2_2_0.xbd, in case someone finds it useful.

Could this problem be fixed in future Xilinx releases?  ML510 boards seem to have been shipped with these RAM modules for a long time (this thread is more than 2 years old).

 

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