11-16-2020 11:43 PM
In my project design, a AXI FULL master design was used to r/w data from/into PS DDR memory. Under normal circumstance, 'BVALID' signal should pull up to complete one writing DDR mem process. But after 100k loop, the 'BVALID' signal start to not work properly and this caused mistake during writing process.
Could u be so kind and help me out on this problem?
11-17-2020 02:10 AM
With only those traces and without looking at your design logic, it's hard to say what your problem is.
In general, were this my problem, I'd start out by placing counters on the various output ports of your AXI master and looking for protocol violations. Particularly, I'd look for WLAST being generated before the last beat of the burst or the logic skipping data at some time when WVALID && !WREADY.
11-17-2020 05:12 PM
Thanks for ur replay, as u can see in the last picture, the WVALID&WREADY&WLAST signal remains in correct order but the BVALID signal has become in disorder
11-17-2020 05:27 PM
The "order" isn't the issue, the counts are. That's why I said I would place counters on the various signals. One of the more common AXI bugs involves dropping beats or even packets. The way to discover this is to count the number of items sent in a series of counters: (AWVALID && AWREADY), (AWVALID && AWREADY ? (AWLEN+1):0), (WVALID && WREADY), (WVALID && WREADY && WLAST), (BVALID && BREADY), etc., and to look for places where the counters don't properly match.
Alternatively, if you'd like to share your design, I'd be glad to look over it to see if I can find any bugs within it. Apart from that, then I'm sorry I don't think I can be of any more help here.