04-15-2008 11:11 PM - edited 04-16-2008 12:37 AM
04-28-2008 09:40 AM
I am also start working on the video topic. I would like to work with you so we can learn from each other.
Regarding your question:
I would like to know if you tried to build the slideshow example from scratch?
I did it already, but I still have a small issue which is my picture is shift down. I don't know if it is because of the size of the image or the signal timming.
05-02-2008 12:06 AM
05-15-2008 02:24 AM
I can know your ideas clearly,because i have ever met this problem before. The difference is i didn't use PPC.
1, you need to write Module to interface the Xilinx DDR PLB IP core, WriteFIFO and ReadFIFO ,just as an arbiter.
2, if PPC is fast enough, you need not to use WriteFIFO. you can interface the Xilinx DDR PLB IP core and ReadFIFO to PPC. Just leave task to PPC.