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Observer
Observer
10,007 Views
Registered: ‎03-14-2008

Using DDR SDRAM module as video memory (XUPV2P)

i want to run C program on PowerPC on Virtex2 Pro, drawing any graphic on the monitor, my controller is 1024x768 60Hz. i will use TwinMOS 512mb CL3 PC3200 DDR SDRAM DIMM module as a video memory.


i will have to use DDR memory as a video memory. and i think that the organization must be as on the picture which i attached to this message. please take a look.

 



So, a C program will run on PPC. PPC will write VGA data on the write FIFO, writeFIFO will write this data to the DDR memory, another readFIFO will read it from the DDR and pass it to the VGActrl state machine, the VGActrl will then write data to the monitor.

i think that two buffers with the specified range must be used, so that they will switch, and there will be no glitches during the image update.

writeFIFO writes data in BUF1, when the BUF1 is full, readFIFO begins reading from BUF1. (shown with blue line) and writeFIFO then writes data to BUF2.

then, when the BUF2 is full, readFIFO begins reading from BUF2, (shown with red line) and writeFIFO then writes data again in BUF1. and so on.

question: how to say to VGActrl state machine that BUF1 (or BUF2) is full, so it can begin reading from it?

it happens continiously and fast, so the image is updated in time and displayed correctly.

i have a 1024x768 and 60Hz VGA controller. so i can calculate the size of the buffers needed.

(1024x768x24) / 8 = 2.359296 MBytes (for one buffer)

the speed of the transfer will be: 2.359296 x 60Hz = 141,55776 MBytes/second

total video memory needed BUF1 + BUF2 = 2.359296 + 2.359296 = 4.718592 MBytes


but the main problem now is in DDR IP core...

can i use Xilinx DDR PLB IP core? (DS425 v 2.00)
will it be possible to use double buffering described above with XIlinx DDR IP core? or i should remake this core? if yes then how?
 
also..i see in my EDK folder ddr_v3_00_a and other versions of the memory controller...however on the Xilinx website i can find only the documentation for the PLB DDR v2.00a (plb_ddr.pdf)... not more.. where to find docs of the other versions of the controller? 

or do i have to write down my own?


ok, please tell me what you think about organization in a whole, and are there errors in my calculations... tell ur opinion. and if its ok, could u advice me what to start with? (i alreadyhave VHDL for the video signal generation) thanks! cya!

i also have created Base System Builder project with EDK.

and added UART and 512MB dual rank memory controller there.

then i created my own peripheral template for PLB bus.

now i am adding my VHDL code to the created peripheral, and importing it again..

i must now interconnect it all correctly. give me idea and hints on how to connect them together? are Read and Write FIFOs are included in DDR IP? or should i create write-to-IP FIFO for video controller peripheral?
 
thank u very much!





Message Edited by migliorin on 04-16-2008 12:37 AM
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Observer
Observer
9,846 Views
Registered: ‎09-06-2007

Hey,

I am also start working on the video topic. I would like to work with you so we can learn from each other.

Regarding your question:

I would like to know if you tried to build the slideshow example from scratch?

I did it already, but I still have a small issue which is my picture is shift down. I don't know if it is because of the size of the image or the signal timming.

 

Thank you,

Thang Nguyen

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Observer
Observer
9,582 Views
Registered: ‎03-30-2008

the two buf should be one for the reader,you can design a buf writer that don't share the highest bits of the writer_address and the read_address signals,both the highes bits input of each are given with the writer,and the reader give the read address signal without the highest bit,and it will read the newest infomation from the full buf for ever ,but it need't to know which one is full.
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Visitor
Visitor
9,072 Views
Registered: ‎05-14-2008

Hi, 

I can know your ideas clearly,because i have ever met this problem before. The difference is i didn't use PPC.

Perhaps,

      1, you need to write Module to interface the Xilinx DDR PLB IP core, WriteFIFO and ReadFIFO ,just as an arbiter.

      Or

     2, if PPC is fast enough, you need not to use WriteFIFO. you can interface the Xilinx DDR PLB IP core and ReadFIFO to PPC. Just leave task to PPC.

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