cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
1,425 Views
Registered: ‎02-09-2010

Using FreeRTOS, PL-PS interrupt function called twice

We are using EMIO to generate a PL to PS interrupt on a Zynq with FreeRTOS. It works, but the interrupt routine is always called twice. Our code is mainly based on

https://forums.xilinx.com/t5/Embedded-Development-Tools/PL-PS-Interrupt-for-Zynq-running-FreeRTOS/td-p/487570

(see accepted solution)

Any idea why the interrupt is called twice?

 

By the way, is it better to use the IRQ_F2P signals? We did not find how to use them with FreeRTOS.

 

Vivado/SDK 2017.4, xc7z030ffg676-2

0 Kudos
5 Replies
Highlighted
1,335 Views
Registered: ‎02-09-2010

Can anybody help?

Thank you

0 Kudos
Highlighted
Explorer
Explorer
1,087 Views
Registered: ‎01-24-2018

Sorry, I cannot help you.

I only wanted to post my experience relating to FreeRTOS and Zynq DMA.

I have a BD that implements DMA in both directions.

The DMA is being handled by a R5 on a ZCU102 eval board.

The R5 communicates the data coming from the fabric to a Linux process running

on the A53 via shared memory.

The Linux application and bare metal R5 code and FPGA perform excellent... never misses a beat.

I have been trying the last couple of days to move the R5 code from bare metal to FreeRTOS.

None of the DMA interrupts work correctly. I get one or more randomly, or none.

Most of my search finds suggestions like check that TLAST is getting generated correctly,

or you need to get the XScuGic instance from FreeRTOS via prvGetInterruptControllerInstance().

My TLAST is great and verified via R5 bare metal.

There is no such call prvGetInterruptControllerInstance();

I can see the FreeRTOS getting a XScuGic and looking it up to set tick interrupt,

but no API to get at it. There just seems to be a lot of misinformation and lack

of a comprehensive enough example to demonstrate the technology.

Disappointing indeed!

 

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
1,043 Views
Registered: ‎09-04-2012

Hi,

Is the behavior apecific to using FreeRTOS? Have you tried using a similar bare metal application to test the interrupt response?

Also, have you veriied using an ILA that the interrupt is only active once and deasserted properly once cleared?

Regards,

Christophe

0 Kudos
Highlighted
Explorer
Explorer
902 Views
Registered: ‎01-24-2018

Re: " Have you tried using a similar bare metal application to test the interrupt response?"

Perhaps you missed this part of my post...

The Linux application and bare metal R5 code and FPGA perform excellent... never misses a beat.

Re: "Also, have you veriied using an ILA that the interrupt is only active once and deasserted properly once cleared?"

No, why would I do that? Why would the interrupt only be "active once".

Precisely how would I clear an interrupt that I am never getting please?

DMA works great in the bare metal application, but not in Xilinx

supported Free RTOS.

0 Kudos
Highlighted
Participant
Participant
351 Views
Registered: ‎06-27-2019

tcachat@metraware.com @jrp Did you every figure out why it was happening and a solution for it? It looks like I'm getting an identical behavior. An edge triggered interrupt is being re-entered in the Zynq.

0 Kudos