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1,791 Views
Registered: ‎02-21-2019

Using PS clock for ILA in Zynq UltraScale+

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Hi,

I am trying to add a debug core to monitor an AXIS and an AXI interface for the Ultra96 board (Zynq UltraScale+ MPSoC device).Screenshot_6.png

I tried both with the System ILA as above and normal ILA.

In both cases, it completes up to implementation without a problem. But when writing bitstream, it gives a warning 

[DRC RTSTAT-10] No routable loads: 36 net(s) have no routable loads. The problem bus(es) and/or net(s) are ....

and the generated bistream does not contain the debug probes.

only related post i found mentioned that the clock to the ILA should be free-running. Does this mean i cannot use the PS clock? If not, should it be okay if i use the reference clock coming to the PS? But i believe then the logic and the ILA will be in two clock domains.

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1,601 Views
Registered: ‎02-21-2019

Despite the warning, the ILA appeared when i programmed the PL from the SDK and refreshed the device in the Vivado Hardware Manager.

View solution in original post

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9 Replies
stephenm
Moderator
Moderator
1,753 Views
Registered: ‎09-12-2007

IF you are using the ps clock for the ila, then you would need to make sure that the PS is configured otherweise the clock is not running.

You can use the psu_init.tcl to config the PSU, or the FSBL.

 

 

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1,749 Views
Registered: ‎02-21-2019

Hi,

The PS is configured. I had even been reading some data that were coming from the Stream FIFO. Then I wanted to debug it because the initial ~FIFO_SIZE+5 number of data were missing always.

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stephenm
Moderator
Moderator
1,747 Views
Registered: ‎09-12-2007

How are you configuring the PS?

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1,734 Views
Registered: ‎02-21-2019

I launch the SDK after generating the bitstream and then configure from there.

I did read somewhere that the PS needs to start first in order for the debug cores to work, because of the clock. But those people did not seem to have problems at bit stream generation stage. 

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stephenm
Moderator
Moderator
1,727 Views
Registered: ‎09-12-2007

How exactly are you configuring the PS in SDK?

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1,723 Views
Registered: ‎02-21-2019

I am sorry, but what do you mean by configuration exactly?

when there are No ILAs, i simply program the bit file from the SDK,
build the BSP and application and then run it with Run As->Launch on Hardware. (I do not usually change any settings/addresses in the BSP).

When i tried with the ILAs i programmed from the Vivado Hardware Manager. But of course, there were no debug probes written.

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bkarsten
Xilinx Employee
Xilinx Employee
1,643 Views
Registered: ‎11-28-2007

Have you verified the reset sourced from the PS is inacitve?

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1,619 Views
Registered: ‎02-21-2019

There was no issue with the reset. The design was sending some output.

Anyway, the activity of the reset does not affect the bit stream generation right?

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1,602 Views
Registered: ‎02-21-2019

Despite the warning, the ILA appeared when i programmed the PL from the SDK and refreshed the device in the Vivado Hardware Manager.

View solution in original post

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