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Explorer
Explorer
2,642 Views
Registered: ‎03-25-2010

Using PlanAhead is the correct way to assign I/O Ports?.

Hello,

 

We are going to design our custom board for a Virtex 5 FPGA.

 

I have some GPIO, uart and I2C ports that I need to assign to I/O's ports.

 

I want to assign them automatically with the PlanAhead. I suppose using PlanAhead autoplace would place pins in a more intelligent way than if I do it manually.

 

Tools > Autoplace I/O Port

 

But I got this message:

------------------------------------------------------------------------------------------

ERROR: "place_ports is only supported for v6 parts planahead".

------------------------------------------------------------------------------------------

 

Using PlanAhead is the correct way to assign I/O Ports?.

 

Thanks.

 

Regards

 

DABG

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Scholar
Scholar
2,638 Views
Registered: ‎02-27-2008

d,

 

Which tool, and what version of that tool, did you create your design in?

 

For example, if you used XPS (EDK), you can assign all the poins in that tool, to the pins you would like them to be on.


If you used ISE, then you can use that tool to assign pins.


To intyelligently assign pins to where the design routes and has its best timing is a bit of experience, and knowledge (some by trial and error).

 

PlanAhead helps you floorplan the design, and its IO, by revealing the physical aspects of your choices in an easy to use fashion.

 

It isn't rocket science:  you would like to have buses and signals grouped together in IO banks located close to their origins if their timing is critical to the performance of your design.

 

Locking down IO pins a priori can make a design unroutable, so sometimes you need to just look at how the design did get routed in FPGA_editor to understand how moving even just one IO might improve the results.

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Professor
Professor
2,626 Views
Registered: ‎08-14-2007

Some tips:

 

Assign the high-speed stuff first.  If you're using external memories like DDR2, let

the MIG tool pick the pins (you can suggest banks based on your layout requirements).

 

Map out your clocks!  Make sure all clock connections go to the proper type of pin and

can connect to the clock regions they support.

 

Build a map of banks and how they physically come off the package.  Determine how the

chip will be placed on the board with respect to other parts to be connnected.  Try to

map the functions so that banks route easily to their loads.

 

Really slow stuff like UART, GPIO, and I2C can be assigned last.  These pins can go pretty much

anywhere you have the right Vcco on the bank.  If you let ISE place these they'll go somewhere

convenient for the placement, but they can usually be moved with little or no impact on your

ability to meet timing with the design.  So better to assign them where they help board level

routing.

 

HTH,

Gabor

-- Gabor
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