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josephg
Observer
Observer
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Registered: ‎05-29-2018

Using a testbench to test an AXI-Lite IP core

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Hello!

 

I have created an AXI-Lite slave with the Vivado IP creator (using the "Create AXI4 Peripheral" option). As the generated code should simply be VHDL code, I thought about testing the IP core using a testbench.

 

Now I would like to read from one register where I modified the output ( instead of reg0 a constant is written to reg_data_out).

 

As far as I understand AXI, the following signals are needed:

axi_arvalid <= '1';

axi_araddr <= "0000"; -- as I would like to read reg0.

 

Sadly there is no output on axi_rdata.

 

The reset is set to 1 and the clock is also working.

 

What am I missing?

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josephg
Observer
Observer
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Registered: ‎05-29-2018

It is working now. I forgot to reset everything at the beginning.

View solution in original post

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bwiec
Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2011
Can you post a screenshot showing the simulation of all the AXI Lite signals?
www.xilinx.com
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josephg
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Observer
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Registered: ‎05-29-2018

Of course.

 

Additionally to the previously mentioned signals I set axi_rready to 1 because I am pretty sure this is necessary.

 

sig.png

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josephg
Observer
Observer
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Registered: ‎05-29-2018

It is working now. I forgot to reset everything at the beginning.

View solution in original post

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