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Javier
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Registered: ‎07-30-2020

Using performance monitor unit to generate an interrupt on ZynqZC706

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I am currently trying to use the performance monitor to generate an interrupt when an overflow of Data Cache misses occurs. I have enabled the pmu and the IRQ for the performance monitor (PMINTENSET is 1 for the counter). I am able to see that the overflow flag is set when the overflow occurs but the interrupt is never triggered. I think I am missing something when setting up the interrupt. I am using Xilinx SDK 2018.2.

I have attached my code for setting up the interrupt:

XScuGic xInterruptController; 	/* Interrupt controller instance */

static void setup_interrupt(void)
{
	uint32_t status;
	XScuGic_Config *pxGICConfig;
	pxGICConfig = XScuGic_LookupConfig( XPAR_SCUGIC_0_DEVICE_ID );
	if (pxGICConfig==NULL)
	{
		xil_printf("\nERROR LOOKING UP CONFIGURATION");
		for(;;);
	}
	status = XScuGic_CfgInitialize( &xInterruptController, pxGICConfig, pxGICConfig->CpuBaseAddress );
	if (status != XST_SUCCESS)
	{
		xil_printf("\nERROR INITIALIZING CONFIGURATION");
		for(;;);
	}

	status = XScuGic_SelfTest(&xInterruptController);
	if (status != XST_SUCCESS)
	{
		xil_printf("\nERROR: SELF TEST FAILURE");
		for(;;);
	}
	/*
	 * Initialize the exception table.
	 */
	Xil_ExceptionInit();

	status = RegisterInterruptExceptions(&xInterruptController);
	if (status != XST_SUCCESS) {
		xil_printf("\nERROR: SetUP Interrupt System Failed");
		for(;;);
	}

	status = XScuGic_Connect( &xInterruptController, XPS_PMU0_INT_ID, (Xil_ExceptionHandler) pmuIRQ_handler, ( void * ) &xInterruptController);
	if (status!= XST_SUCCESS)
	{
		xil_printf("\nERROR CONNECTING INTERRUPT");
		for(;;);
	}

	XScuGic_SetPriorityTriggerType(&xInterruptController, XPS_PMU0_INT_ID, 8, 0b10); // Priority 8 (second highest) and high level sensitivity 

	XScuGic_InterruptMaptoCpu(&xInterruptController, 0, XPS_PMU0_INT_ID);

	// Enable the interrupt for the xTimer in the interrupt controller.
	XScuGic_Enable( &xInterruptController, XPS_PMU0_INT_ID );

}

int RegisterInterruptExceptions(XScuGic *XScuGicInstancePtr)
{

	/*
	 * Connect the interrupt controller interrupt handler to the hardware
	 * interrupt handling logic in the ARM processor.
	 */
	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
			(Xil_ExceptionHandler) XScuGic_InterruptHandler,
			XScuGicInstancePtr);

	/*
	 * Enable interrupts in the ARM
	 */
	Xil_ExceptionEnable();

	return XST_SUCCESS;
}


void pmuIRQ_handler( void *CallbackRef )
{
	xil_printf("Interrupt occurred\n");
}

 

 

I am not sure if I need to use Vivado to map the PMU interrupt to the GIC? I couldn't find any examples on generating interrupts using the performance monitor. I am currently using the default ZC706 HW platform provided by Xilinx SDK and I am not sure if I need to generate a bitstream in Vivado the maps the PMU to the GIC? I thought that this was done by using XScuGic_InterruptMaptoCpu().

I tried with both XPS_PMU0_INT_ID and XPS_PMU1_INT_ID, but neither worked. I tried to follow this post on using shared peripheral interrupts since PMU is this type of interrupt: https://forums.xilinx.com/t5/Processor-System-Design-and-AXI/Using-Private-and-Shared-interrupts-on-Zynq/m-p/773673

Thanks for the help,

Javier

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Javier
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649 Views
Registered: ‎07-30-2020

The bits passed in as high-level sensitivity were incorrect. The parameters should be 0b01 for high-level sensitivity instead of 0b10.

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Javier
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Visitor
650 Views
Registered: ‎07-30-2020

The bits passed in as high-level sensitivity were incorrect. The parameters should be 0b01 for high-level sensitivity instead of 0b10.

View solution in original post

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