cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
1,776 Views
Registered: ‎07-21-2017

VDMA & Genlock Configuration

Hello everyone,

 

I'm currently trying to setting up a system where i'm using the TPG and the AXI VDMA, the purpose is to display a green pattern with HDMI Port.

 

Board -> Avnet ZedBoard

Device -> Zynq 7000 - xc7z020

Video Resolution -> 1920 * 1080p

 

I'm having some issues .

 

This is the configuration of the TPG:

 

TPGConfiguration.png

 

The TPG is configured to display a green pattern, and the VDMA uses both channels, S2MM and MM2S. I have configured the both channel like this:

-> S2MM : Genlock Dynamic-master With TUSER Fsync

-> MM2S : Genlock Dynamic-Slave on Free-Running

The other configurations of the VDMA are:

 

VDMABusConfiguration.png

 

I have already tried by setting up the burst size by 8 bits, nothing changes at all.

 

The issue is located at the AXI4-S to Video Out IP, the locked bit is never activated. The block is configured in Master mode and the VTC is configured for 1080p.

 

AXI4SVidOutConfiguration.png

 

I tried to reduce the video format frequency from 60 Hz to 24/30 Hz, because i thought it was a bandwidth issue between the VDMA and the ZYNQ. I can't see any change.

 

I checked all signals from TPG, from VDMA, from the Converters (RGB to YCrCb and to 4:2:2), from the input of AXI4-S to Vid Out, and all the signals are transmitted correctly, but at the output of the AXI4-S to Vid Out IP, the signals are completely stuck at LOW.

 

After some tests, i realized that the VDMA was the source of the issue, but i don't really know if it's a Genlock configuration issue, an issue from the interconnection between VDMA and DDR (via Zynq 7000), or a software issue.

 

I don't really know what to do at this time.

Does anyone have an idea to resole this issue?

 

Thanks.

0 Kudos
2 Replies
Highlighted
Xilinx Employee
Xilinx Employee
1,726 Views
Registered: ‎08-02-2011

Hello,

For the most part, the setup (at least from hardware) looks pretty good. The one glaring issue is that the vid_io_out_clk on the AXIS2VidOut core needs to be on the same clock domain as the VTC. This could definitely cause it to fail to lock.

www.xilinx.com
0 Kudos
Highlighted
Visitor
Visitor
1,696 Views
Registered: ‎07-21-2017

Hi bwiec & thanks for the answer !

 

I fixed what you said about the vid_out_clk. But the issue is still here, i'm still having black screen.

I was thinking about how the software could cause a lock fail, but i don't really know how this could happen...

 

Cyril

0 Kudos