03-20-2013 03:18 AM
I built a system on zedbeard, it receives video data from an ethernet camera, and store a video frame in DDR memory. Then I use VDMA to read out the frame data into stream, and the stream will be displayed on a VGA monitor with the help of v_tc and stream_to_vid_out core.
by now the data can be received and stored into DDR memory perfectly. and the stream out path seems to be working too. the problem is the video data. I took 2 pictures this morning so you can understand the situation.
the first picture was taken when every thing in the room is static, you see the system is ok if you ignore the aliasing..
while in the second picture my colleague was moving, and you can see the problem, there are a lot of "delay blocks" in the picture. Generally speaking, these blocks were displaying the pixel data from previous frame or few frames earlier. because my colleague was moving to the left, the blocks on him were displaying white, which is the color of the wall in previous frame, and the position where he was in previous frame, is also kind of black.
03-20-2013 03:38 AM
so here is what our system look like
I will attach the mhs as well
we did some test, as you can see, we connected a chipscope monitor to the HP0 port, so we can see whether the data is correct coming out of ps7.
first, we write all FFFFFFFF into the frame buffer in DDR, by using XMD, then we checked , the memory used for frame buffer is full of FFs.. note this is somewhere around 0x10003800
second, we open chipscope to see the bus signals
the bus is in burst mode, so I can only show you 0x10003800 (cursor O) . the bus will burst 256 byte in the following time.
I put cursor X at the position where the data start to become strange. not FFs as desired any more.
so my colleague and I guess the problem come out maybe because of a wrong way of using the HP0 or ps7.. so far we don't have an idea, have anybody seen this situation before?
03-26-2013 07:18 AM
Hi, I have met the simple problem with the Video DMA on Zedboard. When using VDMA to ransfer an image(32bit per pixel), small image such as 1024*250*32 is OK, but a larger one such as 1024*1024*32 always comes with packet loss. I think the problem may be the vdma fifo setting.
My Result Compare:
04-23-2013 08:34 AM
Hello,have your problem fixed or not? I'm very interested in you design,and i want to do like your project ,but i don't know how to start,do you have some tips to me.
04-24-2013 03:35 AM - edited 04-24-2013 03:38 AM
Did you try to increase the values for Linebuffer Depth/Threshold or even the burst length?
In one of their sample designs Xilinx is using a depth=8192 and threshold=8160 for hd-frames.
04-24-2013 01:31 PM
I'm not familiar with the Zedboard, I'm using the ML605 board, with Vitex 6 family FPGA. My design used four (04) HD 1280x720P60 or 1920x1080I30 cameras as inputs via triple SDI, GTX Transceivers at the rate of 1.5 Gbs and CONCURRENTLY DMAing in and out an External DDR3 DDRAM using the 4 pairs of VMDA, AXI4, AXI lite, MIG all being controlled by MicroBlaze processor.
I believed my design throughput is much higher than yours, I have no problem at all (remember I display on an HD Monitor not VGA Monitor).
While configure VDMA IP, I only set the line buffer is 2048 since my scanline is 1280 or 1920 pixels of 20-bit YCrCR, 11-bit line number. burst size is set to maximum 32, Input or Output FIFO depths set to 512.
I don't believe your problem related to the AXI-VDMA bandwidth, look for issue in other part(s) of design.
07-17-2013 11:22 AM
The problem seems to be in the read and write of data from FIFO , Please can you try increasing the read write clock of the FIFO.
When you are trying to push the data out the pixels are not formed properly and unable to form a picture clearly while displaying this is completely a throughput problem.
05-20-2014 06:56 PM
hello, I am a student who is designing a project which is similar to yours. Now, I have achieved some tasks,and I can get images through ov7670 and VGA on the ZedBoard of Xilinx . And ,I have configurated the ov7670 in PL part of Xilinx ZedBoard . however, the images is stored in the SRAM IP . I don't know how to use VDMA to connect the 0v7670 Camera and DDR3 . Also , I do not know how to package my "ov7679 capture ip " to AXI Stream . And ,how to use the Video In/out to AXI Stream ? Please , can you share your project with me . This is my mailbox , firstname.lastname@example.org !
05-22-2015 11:20 AM
hello, i am a biomedical engineer who is currently working with the ov7670 in a project accelerating computer vision algorithms. I have downloaded the project from hamsterworks. However, i am not getting a good image. I am having trouble with the colors. If it is possible, can you share me the code to make it work. I am sending you a picture with the colors i am getting. Thanks...
06-14-2017 04:27 AM
Also have troubles while connecting OV7670 to DDR3 on Zybo. I'm trying to make a ring buffer using VDMA like in this article:
But it still doesn't work for me.
Is there anyone who has successfully made a similar design?