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Registered: ‎10-19-2010

VFBC interface to my custom IP

Hi there :-)


I am using a Spartan 3A DSP board ( xc3sd3400a-4fg676 ) for image processing applications along with the Video Starter Kit. 


I want to access the image stored in the external memory through VFBC connected to my MPMC. 

I wrote a basic verilog code consisting the interface signals for VFBC initiator.

I wrote the MPD and PAO file and exported it as a pcore to my EDK project.

However I am not able to generate the bitstream for the design. 

The error says MDT-Platgen failed with errors.

Could you please help me solve the error?


Thanks a lot.

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2 Replies
Xilinx Employee
Xilinx Employee
Registered: ‎08-01-2007

The flow you did is correct, but we need the detailed error information to help you identify the problem

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Registered: ‎10-19-2010

Hi Joshualu :-)


Thank you for the reply, 

I was able to solve the problem. The model is synthesizing. There was a small mismatch between my MPD and verilog files so it was not synthesizing. Now it s solved.


Thank you,

Have a nice day :-)

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