04-26-2020 02:37 PM
Hi, I'm not 100% sure that this is the right forum, but I'm really hoping that someone here can help me out! If this is the wrong forum, let me know where else I can look for help. I'm relatively new to FPGA design overall, so maybe these questions will come off as a little basic.
In my application, I had a block design with 3 instances of AXI Uartlite and 1 instance of the XADC Wizard. I was originally programming things in Xilinx SDK, and processing incoming data serially, but after some discussion with my team, we decided that we needed to parallelize the computation.
Therefore, I need to create some module in Vivado that can read the recently converted data from the XADC and also read from the UART FIFO buffers. It also needs to interface with some digital inputs and process the data on the positive edge of the signal. I think I have an understanding of how to do the last part, but I'm unsure of how to interface with the XADC and the AXI Uartlite blocks.
Also, I assume that in order to bring the data to the processing system, there needs to be a connection formed to the AXI Interconnect so that I can process the data through the processing system through code in the SDK later? Let me know if this assumption is correct.
Can anyone give me tips on how to get started? Any help is greatly appreciated.
05-16-2020 08:46 PM
08-21-2020 11:10 PM
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