cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
mikewu4466
Observer
Observer
536 Views
Registered: ‎03-07-2019

Verilog Development with XADC and Uartlite

Hi, I'm not 100% sure that this is the right forum, but I'm really hoping that someone here can help me out! If this is the wrong forum, let me know where else I can look for help. I'm relatively new to FPGA design overall, so maybe these questions will come off as a little basic.

blockdesign.PNG

In my application, I had a block design with 3 instances of AXI Uartlite and 1 instance of the XADC Wizard. I was originally programming things in Xilinx SDK, and processing incoming data serially, but after some discussion with my team, we decided that we needed to parallelize the computation.

Therefore, I need to create some module in Vivado that can read the recently converted data from the XADC and also read from the UART FIFO buffers. It also needs to interface with some digital inputs and process the data on the positive edge of the signal. I think I have an understanding of how to do the last part, but I'm unsure of how to interface with the XADC and the AXI Uartlite blocks.

Also, I assume that in order to bring the data to the processing system, there needs to be a connection formed to the AXI Interconnect so that I can process the data through the processing system through code in the SDK later? Let me know if this assumption is correct.

Can anyone give me tips on how to get started? Any help is greatly appreciated.

Regards,

Michael

Tags (3)
0 Kudos
2 Replies
katsuki
Xilinx Employee
Xilinx Employee
454 Views
Registered: ‎11-05-2019

 

Hello @mikewu4466 

I think it's better to try the sample program that comes with the XSDK.

Capture.PNG

Thank you
Don't forget to reply, kudo, and accept as solution.


Don’t forget to reply, kudo, and accept as solution. If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
0 Kudos
katsuki
Xilinx Employee
Xilinx Employee
344 Views
Registered: ‎11-05-2019

 

Hi @mikewu4466 

 

If already issue has resolved, please Give Kudo or Mark the Answer as Accept as Solution and close this thread.

If you have any questions, you can post them.

 

Thank you.


Don’t forget to reply, kudo, and accept as solution. If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
0 Kudos