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Registered: ‎10-15-2017

Video Pipeline Master Timing Mode Question

I am working on a video processing pipeline on a Zynq 7010 SoC. My setup consists of a 1248x1024 resolution camera which runs at 15 fps feeding into the Video In to AXI-Stream IP block. This then feeds into the VDMA block which writes the frames to memory. The VDMA block then reads the frames back to the Video Scaler which then goes into the AXI-Stream to Video Out block which is feeding a 1024x768 VGA monitor with a 60 Hz update rate.

 

I am also using the Video Timing Controller to generate the sync signals for the Video Output Block. Initially, I was also trying to use the VTC to detect the incoming video stream's sync signals. However, I ran into a setup time issue where the registers passing values from the Video In block to the VTC was running on a different clock than the VTC clock. I found the following diagram in the Video Out documentation which seems to suggest that two different clock frequencies can be used with the VTC, but I have yet to find a way to actually do this.Capture.PNG

My Video In block was running off of a clock signal output from the camera. The VTC was running off a 65 MHz pixel clock to generate the timing signals for the Video Out appropriately. I fail to see how the VTC can utilize both Video In and Video Out clocks given it only has the clk input for all Video Timing interfaces.

 

Any insight would be appreciated.

 

Thanks!

 

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