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gi4you
Contributor
Contributor
1,018 Views
Registered: ‎09-24-2009

Virtex Ultrascal QSPI bootloader XIsf_Initialize failure

Hello,

I am trying to boot MicroBlaze application from the QSPI flash memory(Spansion, S25FL512S). The FPGA is Virtex Ultrascal version.


I tested the SPI bootloader application from the Vivado/SDK 2018.2 and Vivado/SDK 2019.1 but the same errors.


The SDK Flash programmer can flash write my golden.bin and ublaze srec file without errors.

The xilisf BSP configuration as below.

BEGIN LIBRARY
PARAMETER LIBRARY_NAME = xilisf
PARAMETER LIBRARY_VER = 5.11
PARAMETER PROC_INSTANCE = system_i_sys_mb
PARAMETER serial_flash_family = 5
END

 

bootloader.c

/*
* Initialize the Serial Flash Library.
*/
Status = XIsf_Initialize(&Isf, &Spi, ISF_SPI_SELECT, IsfWriteBuffer);
if(Status != XST_SUCCESS) {
     print ("\r\nXIsf_Initialize FAILURE\r\n");
     return XST_FAILURE;
}

 

Thanks,

 

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7 Replies
katsuki
Xilinx Employee
Xilinx Employee
954 Views
Registered: ‎11-05-2019

 

Hello @gi4you 

Microblaze accesses the QSPI memory via the AXI-QSPI IP. In addition, Microblaze accesses the DRR memory.
Is your design capable of the above?  If you can share your block design, Forum members will find it easier to confirm.
The following materials may be useful to you.

  • XAPP1280 UltraScale FPGA Post-Configuration Access of SPI Flash Memory using STARTUPE3
  • AR#63605 SDK - How to Create an MCS Boot Image using SPI SREC BootLoader

Thank you
Don't forget to reply, kudo, and accept as solution.


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gi4you
Contributor
Contributor
938 Views
Registered: ‎09-24-2009

Hello katsuky,

Thank you for your reply.

>>Microblaze accesses the DRR memory.Is your design capable of the above?
Yes, I create a project for the DDR-4 memory test, it already passed at uBlaze and I removed DDR IP from the project to make a small project.
I can use UART Lite, UART 16550, IIC IP cores without any problems.

I have experience and used for my project the QSPI booting (AR#63605 SDK) application for the Arty-A7 board and well understood how-to procedure.
This new project, my Vertex Ultrascal board is a non-Xilinx evaluation board and designed by a third party company.

The main difference is EMCCLK clock source, I reviewed the Xilinx Kintex, Vertex evaluation board (KCU105, VCU108, VCU118) the EMCCLK is 90 MHz, and free-running circuit.
But my board the EMCCLK is 80 MHz and clock output controlled by an FPGA program DONE signal.

For example, when power up DONE signal is LOW (before bitstream loading) this time EMCCLK OSC output is available.
After the DONE signal goes to HIGH the EMCCLK output is shutdown (not available EMCCLK any more). Only EMCCL clock is available to boot time.
I need to access QSPI flash memory from the bootloader and SDK user application for reading/write my data.

Here is I/O pin map for the QSPI and qspi clock reference is EMCCLK 80 MHz.
inout qspi1_io0_io,
inout qspi1_io1_io,
inout qspi1_io2_io,
inout qspi1_io3_io,
inout qspi1_sck_io, //EMCCLK 80 MHz
inout [0:0]qspi1_ss_io,


IOBUF qspi1_io0_iobuf
(.I(qspi1_io0_o),
.IO(qspi1_io0_io),
.O(qspi1_io0_i),
.T(qspi1_io0_t));
IOBUF qspi1_io1_iobuf
(.I(qspi1_io1_o),
.IO(qspi1_io1_io),
.O(qspi1_io1_i),
.T(qspi1_io1_t));
IOBUF qspi1_io2_iobuf
(.I(qspi1_io2_o),
.IO(qspi1_io2_io),
.O(qspi1_io2_i),
.T(qspi1_io2_t));
IOBUF qspi1_io3_iobuf
(.I(qspi1_io3_o),
.IO(qspi1_io3_io),
.O(qspi1_io3_i),
.T(qspi1_io3_t));
IOBUF qspi1_sck_iobuf
(.I(qspi1_sck_o),
.IO(qspi1_sck_io),
.O(qspi1_sck_i),
.T(qspi1_sck_t));
IOBUF qspi1_ss_iobuf_0
(.I(qspi1_ss_o_0),
.IO(qspi1_ss_io[0]),
.O(qspi1_ss_i_0),
.T(qspi1_ss_t));

.qspi1_io0_i(qspi1_io0_i),
.qspi1_io0_o(qspi1_io0_o),
.qspi1_io0_t(qspi1_io0_t),
.qspi1_io1_i(qspi1_io1_i),
.qspi1_io1_o(qspi1_io1_o),
.qspi1_io1_t(qspi1_io1_t),
.qspi1_io2_i(qspi1_io2_i),
.qspi1_io2_o(qspi1_io2_o),
.qspi1_io2_t(qspi1_io2_t),
.qspi1_io3_i(qspi1_io3_i),
.qspi1_io3_o(qspi1_io3_o),
.qspi1_io3_t(qspi1_io3_t),
//
.qspi1_sck_i(qspi1_sck_i),
.qspi1_sck_o(qspi1_sck_o),
.qspi1_sck_t(qspi1_sck_t),
//
.qspi1_ss_i(qspi1_ss_i_0),
.qspi1_ss_o(qspi1_ss_o_0),
.qspi1_ss_t(qspi1_ss_t)

xdc file

#
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design]
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN div-1 [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
set_property BITSTREAM.CONFIG.SPI_OPCODE 8'h6B [current_design]
set_property CONFIG_MODE SPIx8 [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN Pulldown [current_design]
#
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property CFGBVS GND [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]

create_clock -name qspi1_sck_io -period 12.500 [get_ports qspi1_sck_io]
create_clock -name CLK_IN1_D_0_clk_p -period 6.400 [get_ports CLK_IN1_D_0_clk_p]
# QSPI1
set_property PACKAGE_PIN AM26 [get_ports qspi1_io0_io]
set_property IOSTANDARD LVCMOS18 [get_ports qspi1_io0_io]
set_property PACKAGE_PIN AN26 [get_ports qspi1_io1_io]
set_property IOSTANDARD LVCMOS18 [get_ports qspi1_io1_io]
set_property PACKAGE_PIN AL25 [get_ports qspi1_io2_io]
set_property IOSTANDARD LVCMOS18 [get_ports qspi1_io2_io]
set_property PACKAGE_PIN AM25 [get_ports qspi1_io3_io]
set_property IOSTANDARD LVCMOS18 [get_ports qspi1_io3_io]
set_property PACKAGE_PIN BF27 [get_ports {qspi1_ss_io}]
set_property IOSTANDARD LVCMOS18 [get_ports {qspi1_ss_io}]
###
### EMCCLK 80 MHz, only available bitstream download (before DONE)
set_property PACKAGE_PIN AL27 [get_ports {qspi1_sck_io}]
set_property IOSTANDARD LVCMOS18 [get_ports {qspi1_sck_io}]

Thank you for your support.

qspi_config.PNG
vcu108_emcclk.PNG
top.PNG
sdk.PNG
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katsuki
Xilinx Employee
Xilinx Employee
840 Views
Registered: ‎11-05-2019

 

Hello @gi4you 

The SREC Boot Loader reads SREC from QSPI memory and writes them to DDR.

The Microblaze jumps to the DDR it has written to and runs the program. So, I think you need DDR in your design.

Thank you


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gi4you
Contributor
Contributor
789 Views
Registered: ‎09-24-2009

Hello,


My board is HTG-940 Virtex Ultrascal board from Hightech company.
Flash model is Spansion S25FL512SA.

I read some information from the "xilisf.h", this library supports the Spansion S25FL512SA model?


* This library supports the Spansion (S25FLXX) devices, but this family hasn't
* been tested. The support for this family of devices is limited to the common
* commands supported by the other flash families.


* - Spansion S25FL
* The Spansion S25FL Serial Flash is divided into sectors of 64 KB and
* in devices like S25FL128/129, the sectors are divided into sub-sectors.
* Each Sector consists of multiple pages. Each Page contains 256 Bytes. The
* Number of Blocks vary for different devices within this family.
*
* The following Spansion flash memories are supported by this library.
* S25FL004 S25FL008 S25FL016
* S25FL032 S25FL064 S25FL128/129

* 5.10 tjs 11/30/17 Added S25FL-L series flash parts support. CR# 987566

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katsuki
Xilinx Employee
Xilinx Employee
754 Views
Registered: ‎11-05-2019

Hello @gi4you 

Did the AXI-QSPI sample program work?

Thank you


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gi4you
Contributor
Contributor
746 Views
Registered: ‎09-24-2009

Hello,


>>Did the AXI-QSPI sample program work?
Where can I find an example?

I believe my QSPI IP interface is fine with QSPI flash chip, I already tested the QSPI bootloader program with ARTY board.

>>I read some information from the "xilisf.h", this library supports the Spansion S25FL512SA model?
Previous, my question is “xiLisf.h” support the Spansion S25FL512SA?

Thanks,

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katsuki
Xilinx Employee
Xilinx Employee
692 Views
Registered: ‎11-05-2019

Hello @gi4you 

I'm not sure, since I don't have the Spansion S25FL512SA.

Regarding exmaple program, you can try it from the XSDK.

a.PNG

Thank you


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