cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
4,895 Views
Registered: ‎04-19-2014

Vivado 2014.2 AXI DMA asserting TREADY without a transaction

First a little bit of background on how I have everything configured. I have a custom IP that has an AXIS FIFO attached to an AXI DMA S2MM channel. When my custom IP receives a packet from the outside world it stores it in the FIFO and increments a pending packet counter and then it triggers an interrupt. The CPU then reads the FIFO length and number of pending packets from my custom IP and uses that information to construct the appropriate S2MM AXI DMA transactions. Once a packet has left the FIFO the pending packet counter is decremented. Pretty straight forward.

 

The problem that I'm experiencing is that the AXI DMA core has TREADY asserted even though the DMA core is halted and does not have any transactions enqueued. I'm assuming it's filling its own internal buffer. As a result the DMA core gobbles up the first 37 bytes from my FIFO before a DMA transaction has even began. This is causing several issues for me.

 

1) If I received a packet longer than 37 bytes and I construct the S2MM DMA transaction using the FIFO length, my buffer is 37 bytes too small which causes an error in the AXI DMA core.

 

2) If I receive a packer smaller than 37 bytes in my FIFO, the AXI DMA core gobbles it up before I have time to read the pending packet counter and FIFO length. As a result I can't be sure if I really received a packet and how long it is.

 

3) If I receive multiple packets smaller than 37 bytes in total, they are gobbled up from the FIFO before the IRQ handler has time to read the pending packet counter and FIFO length.

 

So my question is, how do I make the AXI DMA core only assert TREADY when the channel has been started?

 

One of my potential fixes was to have my custom IP have a register I set that I then OR with the TREADY from the AXI DMA core so I can control when the FIFO starts transmitting, though I think this is a horrible hack.

 

Any help would really be appreciated.

 

p.s

 

Here are some logs showing the issue I'm seeing.


 

xilinx-dma 40400000.axi-dma: Current Control register for channel 1: 0x10002
xilinx-dma 40400000.axi-dma: Set coalesc to 1 for channel 1
xilinx-dma 40400000.axi-dma: Set delay to 0 for channel 1
xilinx-dma 40400000.axi-dma: Channel 1 Control Register 0x10002
  Start: 0, Reset: 0
  Keyhole: 0, Cyclic BD En: 0
  IOC IRQ En: 0, Delay IRQ En: 0, ERR IRQ En: 0
  IRQ Threshold: 1, IRQ Delay: 0
xilinx-dma 40400000.axi-dma: Channel 1 Status Register 0x10009
  Halted: 1, Idle: 0
  SG Enabled: 1
  DMA Internal Error: 0, DMA Slave Error: 0, DMA Decode Error: 0
  SG Internal Error: 0, SG Slave Error: 0, SG Decode Error: 0
  IOC IRQ: 0, Delay IRQ: 0, Error IRQ: 0
  IRQ Threshold: 1, IRQ Delay: 0
xilinx-dma 40400000.axi-dma: Channel 1 Current Descriptor 0x0, Tail Descriptor 0x0
xilinx-dma 40400000.axi-dma: New Control register for channel 1: 0x10002


 

I have my IP configured in loopback mode so I can send a packet via channel 0 and receive it on channel 1. This is the transmission of the packet on channel 0.

 

maple_bus 43c10000.rxMapleBus: maple_bus_net_xmit_frame starting transmit of skb 0xc0b0cb00

maple_bus 43c10000.rxMapleBus: Control Register: 0x00000067
  TX Enabled: 1, RX Enabled: 1, Loopback Enabled: 1
  Reset TX: 0, Reset RX: 0
  TX IRQ Enabled: 1, RX IRQ Enabled: 1
maple_bus 43c10000.rxMapleBus: Status Register: 0x00000000
  TX IRQ: 0, RX IRQ: 0
  TX Buffered Packets: 0, TX Buffer Length: 0
  RX Buffered Packets: 0, RX Buffer Length: 0


maple_bus 43c10000.rxMapleBus: maple_bus_xmit_prepare starting
xilinx-dma 40400000.axi-dma: Number of bytes to copy 1024
xilinx-dma 40400000.axi-dma: Submitting Transaction 0xf000f050 on channel 0
xilinx-dma 40400000.axi-dma: Starting DMA channel 0
xilinx-dma 40400000.axi-dma: Channel 0 Control Register 0x17003
  Start: 1, Reset: 0
  Keyhole: 0, Cyclic BD En: 0
  IOC IRQ En: 1, Delay IRQ En: 1, ERR IRQ En: 1
  IRQ Threshold: 1, IRQ Delay: 0
xilinx-dma 40400000.axi-dma: Channel 0 Status Register 0x10008
  Halted: 0, Idle: 0
  SG Enabled: 1
  DMA Internal Error: 0, DMA Slave Error: 0, DMA Decode Error: 0
  SG Internal Error: 0, SG Slave Error: 0, SG Decode Error: 0
  IOC IRQ: 0, Delay IRQ: 0, Error IRQ: 0
  IRQ Threshold: 1, IRQ Delay: 0

xilinx-dma 40400000.axi-dma: Channel 0 started

maple_bus 43c10000.rxMapleBus: maple_bus_net_xmit_frame completed transmit of skb 0xc0b0cb00


 

This is the IRQ from the AXI DMA saying the MM2S transfer was complete

 

xilinx-dma 40400000.axi-dma: Channel 0 Descriptor 0xf000f000
  Bytes Transfered: 1024
  DMA Internal Error: 0, DMA Slave Error: 0, DMA Decode Error: 0
xilinx-dma 40400000.axi-dma: Transfered 1024 bytes on channel 0
xilinx-dma 40400000.axi-dma: Channel 0 Control Register 0x10003
  Start: 1, Reset: 0
  Keyhole: 0, Cyclic BD En: 0
  IOC IRQ En: 0, Delay IRQ En: 0, ERR IRQ En: 0
  IRQ Threshold: 1, IRQ Delay: 0
xilinx-dma 40400000.axi-dma: Channel 0 Status Register 0x1000a
  Halted: 0, Idle: 1
  SG Enabled: 1
  DMA Internal Error: 0, DMA Slave Error: 0, DMA Decode Error: 0
  SG Internal Error: 0, SG Slave Error: 0, SG Decode Error: 0
  IOC IRQ: 0, Delay IRQ: 0, Error IRQ: 0
  IRQ Threshold: 1, IRQ Delay: 0

xilinx-dma 40400000.axi-dma: IRQ Handled on channel 0


 

 

At this point my IP receives the packet in the RX FIFO and triggers an interrupt


maple_bus 43c10000.rxMapleBus: maple_bus_irq starting
maple_bus 43c10000.rxMapleBus: Control Register: 0x00000067
  TX Enabled: 1, RX Enabled: 1, Loopback Enabled: 1
  Reset TX: 0, Reset RX: 0
  TX IRQ Enabled: 1, RX IRQ Enabled: 1
maple_bus 43c10000.rxMapleBus: Status Register: 0x00000003
  TX IRQ: 1, RX IRQ: 1
  TX Buffered Packets: 0, TX Buffer Length: 0
  RX Buffered Packets: 1, RX Buffer Length: 987
maple_bus 43c10000.rxMapleBus: maple_bus_irq tx IRQ received
maple_bus 43c10000.rxMapleBus: maple_bus_irq rx IRQ received
maple_bus 43c10000.rxMapleBus: maple_bus_start_rx starting
maple_bus 43c10000.rxMapleBus: maple_bus_start_rx buffer has 1 packets of size 987
maple_bus 43c10000.rxMapleBus: maple_bus_enqueue_rx starting

 

As you can see I started off transmitting 1024 bytes but my FIFO reports only 987. If I enque a S2MM transfer for 1024 bytes I receive the full packet. So the AXI DMA core has buffered them.

 

If you read this far thanks ;)

0 Kudos
1 Reply
Highlighted
Teacher
Teacher
4,810 Views
Registered: ‎03-31-2012

to me it seems that tready is not the issue but tvalid is. the slave is allowed to pull up its tready at any time. you should control the tvalid after the fifo by inserting a block between the fifo & the dmac where you first record all incoming fifo packets (ie record their sizes) and then give them to dmac by enabling the tvalid signal.
actually i am not clear on why you can not monitor the output of the fifo and make this recording as things currently stand. You should be able to observe each packet and its size as it's being transferred from fifo to the dmac.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.