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tim_severance
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Registered: ‎03-03-2017

Vivado/Vitis 2019.2 Zynq DDRless FSBL setup

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I am using Vivado/Vitis 2019.2 and for hardware I am using a Digilent Arty Z7 board (which does have DDR), but I am using this setup to prepare for hardware where I will not have DDR placed in the design.

I setup the Vivado block design as shown below in Image 1 (with DDR and AXI disabled).   Question 1: If my design will not technically use the PS for anything, do I still need a block design like this?

Image 1:

entire_block_design.png

 

My top module is shown below:

 

module Top(
    input wire clk_125M,
    output reg led0 = 1'b0
    );
    
    // Include the block design
    design_1_wrapper design_1_wrapper_INST();
    
    reg [31:0] clk_125M_counter = 32'd0;
    
    always @ (posedge clk_125M) begin
        if (clk_125M_counter >= 32'd125_000_000) begin
            clk_125M_counter    <= 32'd0;
            led0                <= ~led0;
        end else begin
            clk_125M_counter    <= clk_125M_counter + 1;
        end
    end
endmodule

As you can see I am creating a simple design with a blinking LED and I want to use the PS only for loading the PL from FLASH.

 

I implemented, generated bitstream, exported the hardware including bitstream and launched Vitis.

In Vitis I created a Platform using the exported Top.xsa setup as Standalone and ps7_cortexa9_0 with Generate Boot Components checked.

I clicked Modify BSP Settings in the standalone section and checkmarked xilffs in order to use this BSP for the FSBL.

My Platform section now says "Out-Of-Date" so I built the platform code.

Once the build completed I did a File->New Application Project, called it fsbl, selected the "Platform" I generated.  For the domain I selected "standalone on ps7_cortexa9_0, and the language C.   I then selected Zynq FSBL and clicked Finish.   

I next build everything and end up with Vitis looking like shown below in Image 2.

Image 2:

vitis_after_build.png

 

Next I right click fsbl_system and click Create Boot Image.    I click Create Image with the setup shown below in Image 3.

Image 3:

create_boot_image_setup.png

Next I want to program this to the flash on the hardware, so I click Xilinx->Program Flash and use the setup shown below in Image 4.

Image 4:

program_flash_setup.png

I get the error shown below.

 

****** Xilinx Program Flash
****** Program Flash v2019.2 (64-bit)
  **** SW Build 2708876 on Wed Nov  6 21:40:23 MST 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.


WARNING: Failed to connect to hw_server at TCP:127.0.0.1:3121
Attempting to launch hw_server at TCP:127.0.0.1:3121

Connected to hw_server @ TCP:127.0.0.1:3121
Available targets and devices:
Target 0 : jsn-Arty Z7-003017A5C514A
	Device 0: jsn-Arty Z7-003017A5C514A-4ba00477-0

Retrieving Flash info...

Initialization done, programming the memory
Using default mini u-boot image file - C:/Xilinx/Vitis/2019.2/data\xicom\cfgmem\uboot\zynq_qspi_x4_single.bin
===== mrd->addr=0xF800025C, data=0x00000000 =====
BOOT_MODE REG = 0x00000000
Downloading FSBL...
Running FSBL...
Finished running FSBL.
===== mrd->addr=0xF8000110, data=0x000FA220 =====
READ: ARM_PLL_CFG (0xF8000110) = 0x000FA220
===== mrd->addr=0xF8000100, data=0x00028008 =====
READ: ARM_PLL_CTRL (0xF8000100) = 0x00028008
===== mrd->addr=0xF8000120, data=0x1F000200 =====
READ: ARM_CLK_CTRL (0xF8000120) = 0x1F000200
===== mrd->addr=0xF8000118, data=0x000FA240 =====
READ: IO_PLL_CFG (0xF8000118) = 0x000FA240
===== mrd->addr=0xF8000108, data=0x00030008 =====
READ: IO_PLL_CTRL (0xF8000108) = 0x00030008
Info:  Remapping 256KB of on-chip-memory RAM memory to 0xFFFC0000.
===== mrd->addr=0xF8000008, data=0x00000000 =====
===== mwr->addr=0xF8000008, data=0x0000DF0D =====
MASKWRITE: addr=0xF8000008, mask=0x0000FFFF, newData=0x0000DF0D
===== mwr->addr=0xF8000910, data=0x000001FF =====
===== mrd->addr=0xF8000004, data=0x00000000 =====
===== mwr->addr=0xF8000004, data=0x0000767B =====
MASKWRITE: addr=0xF8000004, mask=0x0000FFFF, newData=0x0000767B
Problem in running uboot
Flash programming initialization failed.

ERROR: Flash Operation Failed

From what I could tell from google searching this error code it seems this is an issue with DDR possibly?

 

Does somebody know what I might be doing wrong here?   I understand there is no application in Vitis, but I technically only want to use Vitis to have the PS load the PL and that is it.

Thanks for any advice!

Tim

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johnmcd
Xilinx Employee
Xilinx Employee
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Registered: ‎02-01-2008

Hold on as I'm taking a closer look. Default FSBL will error out without DDR on zynq7.

Be enabling the fsbl define "FSBL_DEBUG_INFO", FSBL prints invalid boot mode with error "0xA008".

Looking at fsbl.h, this error means DDR is missing.

So, modify your fsbl in main.c to:

01.png

and recompile it.

Make sure to use this new FSBL in BOOT.BIN and use this new FSBL when programming

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johnmcd
Xilinx Employee
Xilinx Employee
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Registered: ‎02-01-2008

I'm not sure if it is the problem, but your .bif (used to package boot.bin) looks like it has fsbl in it twice. You should only have:

[bootloader] <path>/fsbl.elf

<path>/myDesign.bit

I presume that you correctly enabled qspi in the PS.

When programming the flash, it will run your fsbl.elf in order to setup the PS.

I haven't used zynq7 in Vitis, but for mpsoc, you can create a new hello world app, create hardware project using your xsa, and leave the option enabled to create boot files. This will create fsbl automatically inside the platform project.

johnmcd
Xilinx Employee
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Registered: ‎02-01-2008

Also, make sure to set the mode pins to JTAG during flash programming.

tim_severance
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@johnmcd ,

   Thanks for the reply.   Can you tell me how I would make sure the QSPI is enabled in the PS?

Thanks.

Tim

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johnmcd
Xilinx Employee
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Registered: ‎02-01-2008

In the PS wizard, MIO Configuration->memory interfaces->quad spi flash

The default for my zc702 board is MIO 1..6 and it is configured for Single SS 4bit IO and Feedback Clk is enabled on MIO8.

Of course you have to make sure to configure for the MIO clks you used in your design.

 

00.png

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tim_severance
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Registered: ‎03-03-2017

@johnmcd ,

  In the block design I double clicked the Zynq, then double clicked the Quad-SPI green block and I have Quad=SPI Flash check marked as shown below.

zynq_setup.png

   I know my setup is valid since I created a typical hello world application and hardware design and I can program the flash with that BOOT.bin/Fsbl.elf just fine and all works.

   For some reason with my DDRless setup, after I create the BOOT.bin/Fsbl.elf and try to load them I get "Problem in running uboot", "Flash programming initialization failed." errors in Vivado.

Tim

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johnmcd
Xilinx Employee
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Registered: ‎02-01-2008

Hold on as I'm taking a closer look. Default FSBL will error out without DDR on zynq7.

Be enabling the fsbl define "FSBL_DEBUG_INFO", FSBL prints invalid boot mode with error "0xA008".

Looking at fsbl.h, this error means DDR is missing.

So, modify your fsbl in main.c to:

01.png

and recompile it.

Make sure to use this new FSBL in BOOT.BIN and use this new FSBL when programming

View solution in original post

tim_severance
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Registered: ‎03-03-2017

@johnmcd ,  Thank you!   That was it!   I got the flash programmed with that fix and the bitstream PL bitstream successfully loaded.

Tim

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tim_severance
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@johnmcd ,

   One more question, and I can move this to another forum post if you want.   I now have the flash working, but if I move the BOOT.bin to the SD card and set the M pins to load from SD card it doesn’t load.   Can you confirm that the SD card loading will work without DDR?   FYI, I did make sure the SD pins were enabled in the Zynq setup.

Thanks.

Tim

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tim_severance
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@johnmcd ,

   If I #define FSBL_DEBUG_INFO and try loading my BOOT.bin from the SD card, I get the output below.

Xilinx First Stage Boot Loader
Release 2019.2  Apr  6 2020-13:23:26
Devcfg driver initialized
Silicon Version 3.1
Boot mode is SD
SD Init Done
Flash Base Address: 0xE0100000

And if I use the same boot.bin in the Flash (which is working), I get the output below.

Xilinx First Stage Boot Loader
Release 2019.2  Apr  6 2020-13:23:26
Devcfg driver initialized
Silicon Version 3.1
Boot mode is QSPI
QSPI Init Done
Flash Base Address: 0xFC000000
Handoff Address: 0x00000000
No Execution Address JTAG handoff
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johnmcd
Xilinx Employee
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SD in a DDRless system is trickier since SD is a non-linear memory.

The current FSBL reads the full PL partition from the SD card and stores it in DDR.

So in a DDRless system, FSBL would need to be customized to read a portion of the PL partition into OCM then program to the PL, and then move to the next portion of the PL partition. So for example, you could modify FSBL to do 32KB chunks.

The image move takes place in image_mover.c PartitionMove() and the function MoveImage() calls sd.c SDAccess().

You could create your own fsbl and single step through it. Just make sure you have a BOOT.BIN sitting on the SD and that the boot mode is set to SD.

tim_severance
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@johnmcd ,

   I tried modifying the code as shown below, and it seems to start transferring data, but eventually steams out and stops transferring.   See below images for code change and terminal output in debug mode.

   I originally tried a transfer size of 32k (i.e. 0x8000) and it transferred 2 lines and the steamed out.

   Any tips on what I am doing wrong?

 

code_change1.pngterminal_output1.png

 

Thanks.

Tim

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apateljfti
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Registered: ‎06-28-2019

Hi Tim/John,

I have similar issue with my custom design with ZYNQ 7007s. I am not using the DDR memory and do not plan to use in future. I currently want PS to boot from the flash. In Vitis, I created a simple helloworld application to make sure my PS is up and running. I also made all the modification as talked about in this forum regarding updating main.c in fsbl and using this new fsbl to create BOOT.bin and to program the flash memory. However, I am unable to get this to work. Is there any other changes you did to make ZYNQ work without DDR memory? Did you had to update anything with linker script or anything else in FSBL?

Also, when I program the FPGA with only bitsteam file (.bit), I am successful and my PL works fine. It's only that my vitis generated BOOT does not work.

I would really appreciate if you point out if I may check.

 

 

 

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