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1,405 Views
Registered: ‎04-21-2017

Watchdog: freeze when reading clock control register on MPSoC

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I'm trying to use the system watchdog on Zynq UltraScale+ MPSoC. I have configured SWDT1 in IP integrator and generated the FSBL with SDK.

 

When testing, the FSBL freezes during boot. I have traced the cause back to the following statement in xsdtps.c, which reads the clock control register:

 

 XWdtPs_ReadReg(InstancePtr->Config.BaseAddress,
				 XWDTPS_CCR_OFFSET);

Removing the watchdog initialization form the FSBL, booting Linux and writing to /dev/watchdog0 also causes a system freeze.

 

Am I missing some initialization or configuration?

 

Thanks!

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2,143 Views
Registered: ‎04-21-2017

It seems like this problem is fixed after applying the patch from AR# 69423:

https://www.xilinx.com/support/answers/69423.html

View solution in original post

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2,144 Views
Registered: ‎04-21-2017

It seems like this problem is fixed after applying the patch from AR# 69423:

https://www.xilinx.com/support/answers/69423.html

View solution in original post

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