What is S_AXI_HP0_FIFO_CTRL interface?

[primoz_beltram]

I am migrating working ZYNQ Z7020 design for our HW product from PlanAhead 14.6 to Vivado 2013.3.

So far so good. I get better results from Vivado (in terms of resource utilization) than in PlanAhead for the same functionality (looks like what they say is true :-)).

What bothers me is S_AXI_HP0_FIFO_CTRL (and HP1, HP2) interface which are enabled as soon as I enable HP AXI port in ZYNQ7 Processing System “Customize Block” configuration.

I did not find any enable/disable option regarding this HP AXI FIFO control interface and also no description/documentation what it is.

In PlanAhead XPS 14.6 there was nothing about it, so I left it unconnected.

Building this design in Vivado 2013.3 produces no Errors/Warning regarding it and also design works OK. It looks like this is some kind of “debug” interface.

I searched on WEB (Xilinx and Google), UG585 (TRM) and PG082 (PS7 v5.3). I did not find any reference to this HP AXI FIFO control interface.

Anybody knows where this S_AXI_HP0_FIFO_CTRL interface is described?

[htsvn · Accepted solution]

Hi,

Looking at the MPD file the FIFO_CTRL interface is enabled when we have C_USE_S_AXI_HP being set.

IO_INTERFACE IO_IF = S_AXI_HP0_FIFO_CTRL, IO_TYPE = XIL_HP_FIFO_CTRL_V1, ISVALID = (C_USE_S_AXI_HP0 == 1)

Looking at table 2-6 of the TRM, it looks S_AXI_HP is called AFI. Table 5-5 of TRM talks about AXI_HP register overview.

--HS

[primoz_beltram]

Thanks for the hints.

What I was looking for is described in TRM chapter 5.3.6 Bandwidth Management Features, Table 5-6. Names in TRM for this isgnals are a little bit different from names used in Vivado IP Integrator (eg SAXIHP0... vs S_AXI_HP0_...).

The header of TRM Table 5-6, could be extended to look like Table 5-8, making search in TRM easier.

Will mark as solved.