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artembond
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Registered: ‎08-28-2015

What is m00_axi_init_axi_txn m00_axi_txn_done m00_axi_error at AXT4 bus?

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What is this? Where should I connect this wires? The "AXI Direct Memory Access" as others cores AXI4 Master from Xilinx have no this wires. 

input wire  m00_axi_init_axi_txn,
output wire  m00_axi_txn_done,
output wire  m00_axi_error,

 

 

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siktap
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Registered: ‎06-14-2012

Hi

Please see the exact descriptions.

 

// Initiate AXI transactions input wire INIT_AXI_TXN,

// Asserts when ERROR is detected output reg ERROR,

// Asserts when AXI transactions is complete output wire TXN_DONE,

 

If you are not using these signals, then you can leave them unconnected.

 

Regards

Sikta

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siktap
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Scholar
17,029 Views
Registered: ‎06-14-2012

Hi

Please see the exact descriptions.

 

// Initiate AXI transactions input wire INIT_AXI_TXN,

// Asserts when ERROR is detected output reg ERROR,

// Asserts when AXI transactions is complete output wire TXN_DONE,

 

If you are not using these signals, then you can leave them unconnected.

 

Regards

Sikta

View solution in original post

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287 Views
Registered: ‎01-06-2020

Yes, I saw the comments too, so how do we remove them?, because asserting it on 0 or 1 doesn't also work.

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