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hulingshen
Visitor
Visitor
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Registered: ‎10-22-2020

What is the processor's command for AXI-Full?

Hello.
I am using XC7Z010. And I have made some cores which communicate with zynq processor by AXI-full.
By the way, I can't find the way to use AXI-full on processor side.
I used "memcpy" function on zynq processor for AXI-full, but it acted like AXI-Lite. Burst didn't act.
I hope to know what the processor's command for AXI-full is.
Thanks.

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katsuki
Xilinx Employee
Xilinx Employee
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Registered: ‎11-05-2019

Hi @hulingshen 

You don't need to be aware of AXI-Full or Lite in programming.
What is the hardware configuration? What is the Interface between Master and Slave? Is it data transfer between PS and PL?
AXI-Lite is mainly used for access that does not require performance, such as R/W of control registers.

Thank you.
Don't forget to Reply, Kudo, and Accept as Solution.


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dgisselq
Scholar
Scholar
547 Views
Registered: ‎05-21-2015


@katsuki wrote:

Hi @hulingshen 

You don't need to be aware of AXI-Full or Lite in programming.


You need AXI full if you want performance!  The Xilinx tools treat AXI-lite as a second class citizen, yielding miserably poor throughput when using it.  This user wants high throughput between the PS and PL, and he wants to be able to use C library calls to achieve it.  The ARM should be capable of it.  Is there a cache setting that needs to be enabled to make this happen?  What would get the ARM to issue burst reads and writes from a memcpy user instruction call?

@hulingshen ,

You might want to check out this post.  I think the throughput numbers are enlightening, although I'll admit it won't do anything towards answering your question other than perhaps giving you some insight into what might be going on.  Personally, I'm looking forward to hearing an answer to this myself.

Dan

vanmierlo
Mentor
Mentor
530 Views
Registered: ‎06-10-2008

AFAIK the arm cores do not issue bursts. Not even the multiple register load and store instructions do, oddly enough. If you want bursts you'll have to use some form of dma.

vanmierlo
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Mentor
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Registered: ‎06-10-2008

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katsuki
Xilinx Employee
Xilinx Employee
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Registered: ‎11-05-2019

Hi @hulingshen 

If you understand or already issue has resolved, Kudo, and Accept as Solution. If you have any questions, you can post them.

Thank you.


Don’t forget to reply, kudo, and accept as solution. If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
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