Showing results for 
Show  only  | Search instead for 
Did you mean: 
Registered: ‎07-05-2018

What's the differences between auto and manual ss mode in ZYNQ SPI master?

In UG585, 17.3.3 Master Mode Data Transfer, the three examples all have same assert/de-assert slave select steps, so what's the differences between auto and manual ss mode?

0 Kudos
3 Replies
Registered: ‎04-13-2015


In the manual mode the S/W controls the level on SS when in auto it's the controller.  In auto mode when the TX FIFO is empty, SS is raised ending the transfer; in manual mode, the TX FIFO can become empty but SS can remain low (SW controlled) allowing the SW to fill the TX FIFO. In manual start, the S/W starts the transfer when in auto start the controller starts the transfer when the first word is written in the TX FIFO.

In the 3 programming examples pay attention the following:

1 - spi.Config_reg [Manual_CS]. is only set in manual mode (example 1 & 2)

2 - spi.Config_reg [Man_start_en]. is only set in manual start (example (1 & 3)

I hope this helps

0 Kudos
Xilinx Employee
Xilinx Employee
Registered: ‎07-12-2018

Hi @areslee,


Manual SS Software selects the manual slave select method by setting the spi.Config_reg0 [Manual_CS] bit = 1.

In this mode, software must explicitly control the slave select assertion/de-assertion.

When the [Manual_CS] bit = 0, the controller hardware automatically asserts the slave select during a data transfer.


Automatic SS Software selects the auto slave select method by programming the spi.Config_reg0 [Manual_CS] bit = 0.

The SPI controller asserts/de-asserts the slave select for each transfer of TxFIFO content on to the MOSI signal.

Software writes data to the TxFIFO and the controller asserts the slave select automatically, transmits the data in the TxFIFO and then de-asserts the slave select.

The slave select gets de-asserted after all the data in the Tx FIFO is transmitted. This is the end of the transfer. Software ensures the following in automatic slave select mode.

• Software continuously fills the TxFIFO with the data bytes to be transmitted, without the TxFIFO becoming empty, to maintain an asserted slave select.

• Software continuously reads data bytes received in the RxFIFO to avoid overflow.

Software uses the TxFIFO and RxFIFO threshold levels to avoid FIFO under- and over-flows.

The TxFIFO Not Full condition is flagged when the number of bytes in TxFIFO is less than the TxFIFO threshold level.

The RxFIFO full condition is flagged when the number of bytes in RxFIFO is equal to 128.


Best Regards
Abhinay PS
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give kudos to a post which you think is helpful and reply oriented.

0 Kudos
Registered: ‎07-05-2018

@ericv @abhinayp


Thank you for replies, so my understand of the 'Assert slave select' step in all 3 examples is:

1. In example 1 & 2, manual ss, the 'Assert slave select' step will pull down the spi0_ss1_O port immediatly to activate the outside spi device, and the 'De-assert slave select' step will pull up the spi0_ss1_O port.

2. In example 3, auto ss, the step 2 'Assert slave select' just store which slave will be selected in the register, the corresponding spi0_ss1_O port will be activated acturally at step 7: Start the data transfer, when the TX FIFO becomeing empty, the spi0_ss1_O port will be pulled up immediatly, the last 'De-assert slave select' step just reset the register.


Am'I right?

0 Kudos