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Explorer
Explorer
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Registered: ‎07-19-2012

When does the Zynq Processor System Reset IP assert the reset signal?

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Hi,

 

I'm using the Vivado IP integrator. By default does the peripheral_reset output on the Processor System Reset module assert the reset signal once at device configuration or does it get asserted periodically in some way? What behavior can I expect from the default reset signals? 

 

Thanks, I appreciate all help

 

Sam

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Xilinx Employee
Xilinx Employee
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Registered: ‎02-01-2008

Take a look at the product guide PG164. Peripheral_reset is synchonised to the clock connected to slowest_sync_clk. Assertion of the ouput reset signals can be triggered by ext_reset_in, aux_reset_in, mb_debug_sys_rst and dcm_locked. If all of the reset source inputs are inactive, dcm_locked is active and slowest_sync_clk is toggling, then the peripheral_reset output will be inactive.

 

The reset module will 'time' all outputs for a clean startup. For example, bus_struct_reset deasserts, followed by peripheral_reset, followed by mb_reset.

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Explorer
Explorer
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Registered: ‎07-19-2012

Yikes, I hope I don't have to set up a simulation to answer this question 

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Xilinx Employee
Xilinx Employee
11,176 Views
Registered: ‎02-01-2008

Take a look at the product guide PG164. Peripheral_reset is synchonised to the clock connected to slowest_sync_clk. Assertion of the ouput reset signals can be triggered by ext_reset_in, aux_reset_in, mb_debug_sys_rst and dcm_locked. If all of the reset source inputs are inactive, dcm_locked is active and slowest_sync_clk is toggling, then the peripheral_reset output will be inactive.

 

The reset module will 'time' all outputs for a clean startup. For example, bus_struct_reset deasserts, followed by peripheral_reset, followed by mb_reset.

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