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nahol
Contributor
Contributor
3,583 Views
Registered: ‎05-31-2016

Word addressing or byte addressing for the IP System Cache ?

Hello, I have read the documentation of System Cache without finding clearly if Word addressing or Byte addressing is used for the IP Core System Cache (I need to be sure, in order to determinate how many bits are used for the offset inside a 32 bit address) ? I assumed it is byte addressing, anyone can confirmed me this ?

 

Best regards,

Mathieu

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balkris
Xilinx Employee
Xilinx Employee
3,569 Views
Registered: ‎08-01-2008

It seems information not provided in the pg131. I will report this so it will fix in future release
Thanks and Regards
Balkrishan
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balkris
Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008

It is generic in nature but since cache line length is fixed at the moment it is 6 bits. But that is not something that affect the user.

 

 The Offset bits are 6 along as line length is 16. Index bits varies with cache size, associativity and line length

Thanks and Regards
Balkrishan
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