we are trying to implement a simple ADC custom design on the PYNQ-Z1, but we are having some issues. In a standalone deploy whenever I try to read data from the aux channels (A0 to A5) I get wrong readings. The only voltages that are read correctly are GND and 3v3.
The design comprises only the PS and the XADC_wiz. The PS was configure using the PYNQ TCL and the ADC was configured using the constraint file available on the github page. The XADC is configured as axi_lite connection, continuous channel sequencer, with alarm offs, auto calibration and 16 samples averaging.
The Vivado part runs fine and the bitstream and hdf are generated correctly with no notable warnings.
Inside SDK we tried to use both xadcps or sysmon libraries, and the xadc is instantiated correctly.
EOS and EOC signals are generated and VCCINT and TEMP are read correctly. Only the AUX and Vp_Vn channels output incorrect reads.
The signal in input is generated using a regulated DAC.