04-15-2017 06:16 AM
I am using Vivado 2016.4 on Ubuntu 16.04 machine, my target boards are either ZC702 or ZedBoard.
My goal is to build a simple AXI-PS/PL data flow pipeline that would process stream of data from the XADC.
The first problem that I encounter is as follows: I want to use AXI-Stream interface of the XADC, but receive no data from the ADC.
My goal architecture is as follows: XADC AXIS --> AXIS FIFO --> filter. Here is the block diagram:
My understanding is as follows: as soon as AXI-Stream slave asserts `tready` signal, the AXI-Stream master should transfer the data. However, on the Chipscope the data and from the master and `tvalid` signals are always `0`.
Here is my Chipscope picture (I see conversion is going on, but no data):
Finally, here is my ADC configuration:
What is wrong with this configuration? How do I approach my problem to get the ADC data as AXI-Stream data flow?
Are there any known issues of using AXI-Stream with XADC?
(P.S. I have looked at xapp1183, it does not solve my problems: first, it is incompatible with current vivado version, second, I was not able to find principal differences of their and my XADC configurations).
04-15-2017 08:46 AM
@kselyunin did you go into the other tabs of the configuration? Maybe there are some settings you need to do on the 'adc setup' tab for automatic enable. Another question is where vp_in and vn_in are connected. Are you sure there is signal on them? Finally checkout the xadc register space and read some of the values to see how they are programmed. If you have data on input, it might be that you are missing some enable control in the register space.
04-15-2017 10:35 AM
My ADC Setup tab looks like follows (essentially default configuration more or less):
VP and VN are connected to the corresponding pins of the XADC connector, in .xdc file (for ZedBoard):
set_property IOSTANDARD LVCMOS33 [get_ports vn_in] set_property PACKAGE_PIN L11 [get_ports vp_in] set_property IOSTANDARD LVCMOS33 [get_ports vp_in] set_property PACKAGE_PIN M12 [get_ports vn_in]
The problem is that data transfer is not started by the XADC IP, since it always outputs `0` on the `tvalid` output -- no valid data is transferred, although it received `1` on the `tready` line. On the chipscope I see that the ADC is doing conversion (i.e. assigning `eoc_out` signal when the data A/D conversion is finished, but I do not see the data flowing. On the ZC702 we are able to read A/D value via AXI-lite interface, so it is working, but there is this problem with the stream.
04-15-2017 12:14 PM
@kselyunin are you running any OS and/or any driver? I think you need to do some access to the axi-lite space and enable the conversion. Also checkout this thread https://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/XADC-Values-not-updating/td-p/571422 which might give you some ideas to explore.