04-03-2019 12:38 AM - edited 04-03-2019 01:41 AM
Hi all,
I've been trying to test XAAP1079 at Vivado 2018.3.
My results may be summed-up as follows:
I've read https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842203/Unsupervised+AMP, and https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842504/XAPP1079+Latest+Information but i didn't find anything that works for me...
I'm also trying to migrate to OpenAMP and Libmetal as shown in UG1189 and at https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841668/Multi-OS+Support+AMP+Hypervisor#Multi-OSSupport(AMP&Hypervisor)-Bare-metal/Bare-metalAMP but it was impossible for me to run a code...
If more information are require, i will provide it.
Thanks in advance,
Victor.
04-10-2019 11:30 PM
04-10-2019 11:39 PM
Hi Ritakur,
Thanks for your response. I will try to debug FSBL as you say. I'm trending to think that the issue is in FSBL, due to I'm using the standard ones which are generated with vivado, and not a modified version of them as describes XAPP1079. I thought that DUSE_AMP=1 flag will allow the compiler to compile the code which was able to manage more than one partition... but guess i was wrong.
Are there any new revision of the XAPP 1079 application nothe where this files are available for downloading, or any kind of documentation where this process had been explained?
Best regards,
Victor.
04-10-2019 11:51 PM
04-11-2019 12:06 AM
It is exactly what i did... I use the FSBL which are generated with Vivado, and use the flag DUSE_AMP=1 at CPU1 BSP.
In order to provide more information, I'm going to insert my the code here:
For ARM0:
void init_CPU1(void) { u32 RegVal; //Disable cache on OCM Xil_SetTlbAttributes(0xFFFF0000, 0x14de2); //Disable cache on fsbl vector table location Xil_SetTlbAttributes(0x00000000, 0x14de2); Xil_Out32(CPU1_CATCH, APP_CPU1_ADDR); Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); // Assert and deassert cpu1 reset and clkstop using above sequence RegVal = Xil_In32(A9_CPU_RST_CTRL); RegVal |= A9_RST1_MASK; Xil_Out32(A9_CPU_RST_CTRL, RegVal); RegVal |= A9_CLKSTOP1_MASK; Xil_Out32(A9_CPU_RST_CTRL, RegVal); RegVal &= ~A9_RST1_MASK; Xil_Out32(A9_CPU_RST_CTRL, RegVal); RegVal &= ~A9_CLKSTOP1_MASK; Xil_Out32(A9_CPU_RST_CTRL, RegVal); // lock the slcr register access Xil_Out32(XSLCR_LOCK_ADDR, XSLCR_LOCK_CODE); CONTROL_FLAG_ARM0 = 0; }
And for ARM1:
void init_sharedMemorySegment_FROM1() { Xil_SetTlbAttributes(SHARED_MEMORY_START_ADDRESS,0x14de2); sleep(2); //xil_printf("DEBUG - AAPv1b - ARM1 - Processor online without debug support\r\n"); } void wakeUp_System() { while(CONTROL_FLAG_ARM0 == 0){}; CONTROL_FLAG_ARM0 = 0; //xil_printf("ARM1 - Processor started and online\r\n"); //return XST_SUCCESS; }
This code is as appear for XAPP 1079.
I use BSP standalone v6.8, which theoretically includes AMP support. AMP flag is asserted for ARM1:
-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra -DUSE_AMP=1
The flash file (.mcs) is generated using the "Create Boot Image" widget:
Previous image is the actual image I'm generating.
If you were so kind as to have a look at the code and generation and give me feedback about something strange or wrong i'll be so grateful...
Thanks for all your support.