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7,700 Views
Registered: ‎04-08-2013

XAPP1082 on Vivado

Hello,

 

Can you provide an updated version of XAPP1082 which works on Vivado?

 

Best regards,

Nicolae Rosia.

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Xilinx Employee
Xilinx Employee
7,675 Views
Registered: ‎10-24-2013

Hi,
I don't think we have Vivado version of this XAPP
Thanks,Vijay
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7,670 Views
Registered: ‎04-08-2013

Do you have any plans on updating it to Vivado?

 

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Explorer
Explorer
7,545 Views
Registered: ‎03-29-2008

Given that Vivado is the recommended design tool for Zynq when will XAPP1082 be ported to Vivado?

 

 

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Observer
Observer
7,388 Views
Registered: ‎06-10-2014

Hello all,

 

I also would be interested in a updated application note. Did you face any issues in running this example on ZC706?

 

We are having problems with linkup, it does not go up, even with "ready to test" exaple files.

 

 

Kind regards

Piotr Zdunek

 

Warsaw University of Technology

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Explorer
Explorer
7,126 Views
Registered: ‎05-22-2008

@vijayak 

 

So I am looking for a Vivado version of this project as well as the following Xilinx webpage seems to indicate that a 3.0 version exists:

 

http://www.wiki.xilinx.com/Zynq+PL+Ethernet

 

So where does one find this?

 

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Xilinx Employee
Xilinx Employee
7,020 Views
Registered: ‎08-26-2009

The v3.0 of XAPP1082 supporting Vivado 2014.4 will be available soon. The package is awaiting approval and will be in pipeline for web release very soon. There might be some delay in seeing it on Xilinx.com due to holiday break coming in between.

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Explorer
Explorer
7,007 Views
Registered: ‎05-22-2008

Thanks @sunitaj ! I'm pretty sure I have it figured out, but having the reference design will help regardless

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Observer
Observer
6,893 Views
Registered: ‎06-10-2014

We are also very keen to see an updated version of 1082 application note. Please let us know when the design will be posted online. 

 

 

Kind regards

Piotr Zdunek

 

Warsaw University of Technology

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Observer
Observer
6,692 Views
Registered: ‎06-10-2014

Thank you for uploading the new design.

 

 

I have one question regarding the design:

GPIO0 via EMIO is used for reseting PCS/PMA core and I can see that the kernel patch that is provided with the design uses this pin. Can an EMIO GPIO be made partially external e.g. can I connect GPIO_0[0:0] to PCS/PMA reset and have GPIO_0[15:1] made external? I know I can do it manually in hdl, but I wonder if it can be done directly in block design.

 

Kind regards

Piotr Zdunek

 

 

Warsaw University of Technology

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Anonymous
Not applicable
3,104 Views

There is a xlslice ip in the ip catalog that you should use. This will let you split the gpio down. Or, you can just select the + on the gpio on the ps in iPi and connect the gpio pin externally
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Observer
Observer
3,064 Views
Registered: ‎06-10-2014

@

 

 

 

 

 

Warsaw University of Technology

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Adventurer
Adventurer
1,945 Views
Registered: ‎01-09-2014

Since I can no longer find XAPP1082 2014.4 files

 

I'm posting 2014.4 compatible scripts - some easy to do changes had to be made

- please diff against 2015.4 version to see the cahnge

 

With Regards

T

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