and check out the PS memory interface on pages 13 for the FPGA and 23 for the DIMM connector you'll see that only CS0 and CS1 are connected on the design. The additional CS pins, CS2 and CS3, which can also act as the Logical Rank Select pins for 3DS devices, C0 and C1, are not connected but that doesn't really matter since the PS only supports dual rank devices. Additionally the PS memory controller doesn't support 4-bit memory devices so you can't use SODIMMs made with those and the layout reflects this by not having provisions for the additional DQS pairs needed for 4-bit designs. Other than that it's a 72-bit interface with 64-bits of data plus 8-bits of ECC but you can also use it as a regular 64-bit without ECC. The PS memory configurator is very flexible so it will support a wide variety of devices.