XPPU error when enabling isolation at FSBL stage 4

[arturo_pg]

This question is very related to the AR#71015. I generated an isolated system following the guidelines explained in:

• wiki: Isolation Configuration Consideration
• XAPP1320 
• UG1209(v2018.1)

and I concluded with this setup:

APU no secure:

APU secure:

PMU:

RPU:

On that system I could:

• Boot Linux on the APU running on the high memory (above 0x8_0000_0000)
• Launch standalone apps on the R5 processors from the SDK

But I couldn't run standalone apps on the R5 processors when booting from the SD running the FSBL on the A53 processors. For this reason, I added the CRL_APB (secure) module to the RPU as explained on the AR#71015. But that solution is not working. Could you check my setup?

I don't know how to do this:

"... or modify the code to route CRL_APB access to the PMUFW using xilpm" (which is the other solution explained on the AR#71015)

If I bypass the isolation configuration in the FSBL, it works.

My final goal is to run Linux from the high memory on the APU and standalone/RTOS apps from the low memory on the RPU while sharing some part of the memory. I could do that using v2017.3 of the Vivado tools when the isolation was not enabled.

[arturo_pg · Accepted solution]

I found the solution:

I had to add the RPU node to the APU-secure subsystem. It is necessary because the FSBL put the R5 cores in Lovec/Hivec in the function XFsbl_UpdateResetVector.

Now I can launch standalone apps on the R5 processors from the SD with isolation enabled.

[stevem]

I noticed you referenced xapp1320.  I just released a major update to that document (revision 2.0).  Additionally, Vivado release 2019.1 has a default "secure system" that address some of these concerns as] well.