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migliorin
Observer
Observer
3,446 Views
Registered: ‎03-14-2008

XUPV2P and its DDR SDRAM

Hello,

In the base system builder i choose to include DDR SDRAM Controller with 512MB dual rank. I choosed the recommended memory module: KVR266X64C25/512. However, when i choose the "configure IP" menu in the System Assembly View in EDK, the Xilinx custom controller has the following DDR parameter: Number of DDR Memory banks: 2 (C_NUM_BANKS_MEM = 2) WHY?

as i see from the description datasheet of this memory module it says that there are 4 memory banks:
=========================================
This document describes ValueRAM's 64M x 64-bit (512MB), CAS Latency 2.5 SDRAM
(Synchronous DRAM) DDR266 memory module. The components on this module include
sixteen 32M x 8-bit (8M x 8-bit x 4 Bank / 133MHz, 7.5ns, CL2.5 components) SDRAM
in TSOP packages.
=========================================

well, i tried to change this number to be 4. However, during the bitstream generation i got the following errors:
===========================================
ERROR:MDT - GLOBAL
PORT:fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE_pin
CONNECTOR:fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE -
E:\PROJECTS\EDK\test27\system.mhs line 35 - 4 bit-width connector assigned to
2 bit-width port
ERROR:MDT - GLOBAL
PORT:fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn_pin
CONNECTOR:fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn -
E:\PROJECTS\EDK\test27\system.mhs line 36 - 4 bit-width connector assigned to
2 bit-width port
Completion time: 1.00 seconds
ERROR:MDT - platgen failed with errors!

make: *** [implementation/system.bmm] Error 2
==========================================

what is the problem?

i also looked at the XUPV2P users guide and saw the following:
-------------------------------------------------------------------------
SDRAM_CKE0 O 21 R26 SSTL2-II
SDRAM_CKE1 O 111 R25 SSTL2-II
------------------------------------------------------------------------
SDRAM_S0_Z O 157 R24 SSTL2-II
SDRAM_S1_Z O 158 R23 SSTL2-II
------------------------------------------------------------------------

here is the piece of my UCF file:
======================
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE_pin<1> LOC=R26;
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE_pin<1> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE_pin<0> LOC=R25;
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE_pin<0> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn_pin<1> LOC=R24;
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn_pin<1> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn_pin<0> LOC=R23;
Net fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn_pin<0> IOSTANDARD = SSTL2_II;
=======================

when i tried to change the range of external port, it worked, but the UART did not show anything...strange...

is it some kind of bug inside the Xilinx implementation of the memory controller for 512MB dual rank memory module?

please say what u think! thanks!
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