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nctuser
Participant
Participant
231 Views
Registered: ‎10-27-2019

Xil_L1DCacheInvalidate() function does not exit.

Hello,

I am working with the Zynq-7000 DDRLESS example project (Zynq-7000 AP
SoC Boot - Booting and Running Without External Memory Tech Tip) and it works
propery when I use according to the TechTip instructions. To fit the DDRLESS
example project to our needs I should made some modifications in the DDRLESS
FSBL and after this modifications I have a strange error.

In the main function (after image loading and before the handoff) there are L1
cache enable and invalidate functions and the program execution sticks at
Xil_L1DCacheInvalidate function and never exits. There are a dual for loop in the
function and this for loop holds the execution.

/*
* Load boot image
*/
HandoffAddress = LoadBootImage();
Xil_L1DCacheEnable();
Xil_L1ICacheEnable();
Xil_L1DCacheInvalidate(); /* <- Never exits. */
Xil_L1ICacheInvalidate();

Two of the modifications what I made and can be important is the DDRLESS FSBL
is not the first code after exit from BootROM (the DDRLESS FSBL finds other the
reset/BootRom conditions) and the DDRLESS FSBL runs from OCM.

Why is even called the Xil_L1DCacheInvalidate again since the Xil_L1DCacheEnable
cache enable function calls the same Xil_L1DCacheInvalidate funciton? If I comment
out the Xil_L1DCacheInvalidate function seemly everythings works as expected but
I do not know is this the proper solution of the problem.

I would like to ask for some advice what can happen here or maybe the symptom
says something for zynq/cortexa9 experts.

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1 Reply
nctuser
Participant
Participant
86 Views
Registered: ‎10-27-2019

I would like to describe the problem again because what I wrote was not what
exactly happened. I still do not know what causes this.

What I do:

xil_printf("\n L1D enable...");
Xil_L1DCacheEnable();
xil_printf("\n L1I enable...");
Xil_L1ICacheEnable();
xil_printf("\n L1D invalidate...");
Xil_L1DCacheInvalidate();
xil_printf("\n L1I invalidate...");
Xil_L1ICacheInvalidate();

And what I see on serial output: the Xil_L1ICacheEnable and Xil_L1DCacheInvalidate
functions are called after each other infinitly.

L1D enable...
L1I enable...
L1D invalidate...
L1I enable...
L1D invalidate...
L1I enable...
L1D invalidate...
L1I enable...
L1D invalidate...
L1I enable...
(and so on...)

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