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amahpour
Observer
Observer
476 Views
Registered: ‎01-28-2015

Xilinx CAN BUS IP Core Simulation from COE files

Hi,

I am using the CAN Bus IP Core and would like to run a testbench. In attempts to decipher the COE files I rewrote the test bench is a human readable format:

// write_reg(address, data)
// read_reg_validate(address, data, mask)

// Set Mode Select Register
write_reg               (base_addr + 'h00000004, 'h00000002);               
// Set Baud Rate Prescaler Register
write_reg               (base_addr + 'h00000008, 'h00000001);               
// Set Bit Timing Register
write_reg               (base_addr + 'h0000000c, 'h000000b8);               
// Set Interrupt Enable Register
write_reg               (base_addr + 'h00000020, 'h00000018);               
// Set Software Reset Register
write_reg               (base_addr + 'h00000000, 'h00000002);               
// Read Interrupt Status Register. Ensure no interrupt occurred.
read_reg_validate       (base_addr + 'h0000001c, 'h00000000, 'h00000008);   
// Write sample data to transmit over TX line
write_reg               (base_addr + 'h00000040, 'h4b200000);               
// Write sample data to transmit over TX line
write_reg               (base_addr + 'h00000044, 'h50000000);               
// Write sample data to transmit over TX line
write_reg               (base_addr + 'h00000048, 'h0eafac43);               
// Write sample data to transmit over TX line
write_reg               (base_addr + 'h0000004c, 'hcb000000);               
read_reg_validate       (base_addr + 'h0000001c, 'h00000002, 'h00000002);
write_reg               (base_addr + 'h00000024, 'h00000002);
read_reg_validate       (base_addr + 'h0000001c, 'h00000080, 'h00000080);
read_reg_validate       (base_addr + 'h00000050, 'h4b200000, 'hffffffff);
read_reg_validate       (base_addr + 'h00000054, 'h50000000, 'hffffffff);
read_reg_validate       (base_addr + 'h00000058, 'h0eafac43, 'hffffffff);
read_reg_validate       (base_addr + 'h0000005c, 'hcb000000, 'hffffffff);
write_reg               (base_addr + 'h00000024, 'h00000080);
read_reg_validate       (base_addr + 'h0000001c, 'h00000000, 'h00000004);
write_reg               (base_addr + 'h00000030, 'h4b200000);
write_reg               (base_addr + 'h00000034, 'h80000000);
write_reg               (base_addr + 'h00000038, 'h0eafac43);
write_reg               (base_addr + 'h0000003c, 'hcb000000);
read_reg_validate       (base_addr + 'h0000001c, 'h00000002, 'h00000002);
write_reg               (base_addr + 'h00000024, 'h00000002);
read_reg_validate       (base_addr + 'h0000001c, 'h00000080, 'h00000080);
read_reg_validate       (base_addr + 'h00000050, 'h4b200000, 'hffffffff);
read_reg_validate       (base_addr + 'h00000054, 'h80000000, 'hffffffff);
read_reg_validate       (base_addr + 'h00000058, 'h0eafac43, 'hffffffff);
read_reg_validate       (base_addr + 'h0000005c, 'hcb000000, 'hffffffff);
write_reg               (base_addr + 'h00000024, 'h00000080);
read_reg_validate       (base_addr + 'h0000001c, 'h00000000, 'h00000004);
write_reg               (base_addr + 'h00000030, 'h4b300000);
write_reg               (base_addr + 'h00000034, 'h00000000);
write_reg               (base_addr + 'h00000038, 'h00000000);
write_reg               (base_addr + 'h0000003c, 'h00000000);
read_reg_validate       (base_addr + 'h0000001c, 'h00000002, 'h00000002);
write_reg               (base_addr + 'h00000024, 'h00000002);
read_reg_validate       (base_addr + 'h0000001c, 'h00000080, 'h00000080);
read_reg_validate       (base_addr + 'h00000050, 'h4b300000, 'hffffffff);
read_reg_validate       (base_addr + 'h00000054, 'h00000000, 'hffffffff);
read_reg_validate       (base_addr + 'h00000058, 'h00000000, 'h00000000);
read_reg_validate       (base_addr + 'h0000005c, 'h00000000, 'h00000000);
write_reg               (base_addr + 'h00000024, 'h00000080);
read_reg_validate       (base_addr + 'h0000001c, 'h00000000, 'h00000004);
write_reg               (base_addr + 'h00000030, 'h4b3fcbae);
write_reg               (base_addr + 'h00000034, 'h80000000);
write_reg               (base_addr + 'h00000038, 'h0fab6cde);
write_reg               (base_addr + 'h0000003c, 'heb4a5d98);
read_reg_validate       (base_addr + 'h0000001c, 'h00000002, 'h00000002);
write_reg               (base_addr + 'h00000024, 'h00000002);
read_reg_validate       (base_addr + 'h0000001c, 'h00000080, 'h00000080);
read_reg_validate       (base_addr + 'h00000050, 'h4b3fcbae, 'hffffffff);
read_reg_validate       (base_addr + 'h00000054, 'h80000000, 'hffffffff);
read_reg_validate       (base_addr + 'h00000058, 'h0fab6cde, 'hffffffff);
read_reg_validate       (base_addr + 'h0000005c, 'heb4a5d98, 'hffffffff);
write_reg               (base_addr + 'h00000024, 'h00000080);
read_reg_validate       (base_addr + 'h0000001c, 'h00000000, 'h00000004);
write_reg               (base_addr + 'h00000030, 'h7cf8deaf);
write_reg               (base_addr + 'h00000034, 'h00000000);
write_reg               (base_addr + 'h00000038, 'h00000000);
write_reg               (base_addr + 'h0000003c, 'h00000000);
read_reg_validate       (base_addr + 'h0000001c, 'h00000002, 'h00000002);
write_reg               (base_addr + 'h00000024, 'h00000002);
read_reg_validate       (base_addr + 'h0000001c, 'h00000080, 'h00000080);
read_reg_validate       (base_addr + 'h00000050, 'h7cf8deaf, 'hffffffff);
read_reg_validate       (base_addr + 'h00000054, 'h00000000, 'hffffffff);
read_reg_validate       (base_addr + 'h00000058, 'h00000000, 'h00000000);
read_reg_validate       (base_addr + 'h0000005c, 'h00000000, 'h00000000);
write_reg               (base_addr + 'h00000024, 'h00000080);

 

My issue is that I am always seeing the CAN TX line stay at HIGH (i.e. it never transmits data). I have a clock generated from PL2 (IOPLL) of my Zynq to run at 23.81 MHz.

Is there any type of smoke test or insight into the core that will allow me to debug if things are working or not?

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1 Reply
nwillard
Contributor
Contributor
418 Views
Registered: ‎10-13-2015

Changing the Mode Select from Confguration to Normal (Reg 0x4 = 0) allowed me to get the TX line to toggle. The test bench needs to be tweaked to successfully complete though.