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tmaintz
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Adventurer
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Registered: ‎12-26-2016

Xilinx FFT "Event_Frame_Started" as PL-PS Interrupt to Zynq PS

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Hi there,

long story short: Is there something special to connect a signal (which is '1' for 1 FPGA clock cycle) as an interrupt to the Zynq PS?

 

Background information:

I would like to transfer some data from PS to PL via DMA when a FFT starts to calculate data. I've connected the FFT output "event_frame_started" via a concat element to the Zynq IRQ_F2P Interrupt input (see attachment). Synthesis works fine, no error messages.

 

I can see the correct behaviour of the "event_frame_started" by an ILA core. But there is no interrupt executed in the PS. Therefore I guess that the PL interrupt might not be recognized by the PS.

 

This is the sourcecode of the PS part to connect the interrupt signals to a callback function (color names in the printf are macros for terminal output):

 

int Zynq_Register_ISR(XScuGic* ISR_Controller_ptr, unsigned int device_intr_address, Xil_InterruptHandler ISR_Ptr, void *ISR_argument)
{

if ( ISR_Controller_ptr == NULL ) return XST_FAILURE;
    if (XScuGic_Connect(ISR_Controller_ptr,
            device_intr_address,
            ISR_Ptr,
            ISR_argument) == XST_SUCCESS)
    {
        XScuGic_Enable(ISR_Controller_ptr, device_intr_address);
        xil_printf("ISR Address %p " GRN " ENABLED" RESET "\n\r",device_intr_address);
    }
    else
    {
        xil_printf("ISR Address %p " RED " FAILED" RESET "\n\r",device_intr_address);
        return XST_FAILURE;
    }

    return XST_SUCCESS;
}

int SetUpInterruptSystem(XScuGic *XScuGicInstantePtr)
{
    Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, (Xil_ExceptionHandler) XScuGic_InterruptHandler, XScuGicInstantePtr);
    Xil_ExceptionEnable(); // enable ISR in ARM
    return XST_SUCCESS;
}


int InitializeInterruptSystem(int deviceID )
{

    if((GicConfig = XScuGic_LookupConfig(deviceID)) == NULL)
    {
        return XST_FAILURE;
    }

    int result = XScuGic_CfgInitialize(&InterruptController, GicConfig, GicConfig->CpuBaseAddress);
    if(result != XST_SUCCESS)
    {
        return XST_FAILURE;
    }

    if (SetUpInterruptSystem(&InterruptController) != XST_SUCCESS)
    {
        return XST_FAILURE;
    }

    return XST_SUCCESS;
} // called by int register_ISR()
{ if (Zynq_Register_ISR(ISR_Controller_ptr, XPAR_FABRIC_XFFT_0_EVENT_FRAME_STARTED_INTR, (Xil_InterruptHandler)FFT_Started_ISR, NULL) == XST_FAILURE) return XST_FAILURE;
return XST_SUCCESS;
} // callback function of the event started interrupt void FFT_Started_ISR(void* arg) { xil_printf("%s\n\r",__func__); Xil_Out32( XPAR_AXI_DMA_1_BASEADDR + MM2S_SourceAddress, (unsigned int)start_address ); Xil_Out32( XPAR_AXI_DMA_1_BASEADDR + MM2S_Length, length); }

int main(void)
{
init_platform();
    ps7_post_config();
if(InitializeInterruptSystem( XPAR_PS7_SCUGIC_0_DEVICE_ID ) == XST_SUCCESS)
    {
        xil_printf(RED "ISR System Initialized\n\r" RESET);
    }
    else
    {
        xil_printf(GRN "ISR System ERROR\n\r" RESET);
    }

    if(register_ISR() != XST_SUCCESS)
    {
        xil_printf(RED "DMA_Init_with_ISR\tFAILED\n\r" RESET);
    }

while(1) {}
return 0;
}

Thanks for any replies!

 

If you need further information don't hesistate ;)

 

Greetings,
Thomas

 

IRQ_Connection.jpg
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1 Solution

Accepted Solutions
tmaintz
Adventurer
Adventurer
974 Views
Registered: ‎12-26-2016

The AXI Interrupt Controler is the answer ;)

Setting this Core to level detect mode helps me out.

 

Sorry for answering my own posts!

 

Greetings,
Thomas

View solution in original post

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tmaintz
Adventurer
Adventurer
896 Views
Registered: ‎12-26-2016

Here's the ILA output connected to the FFT Core output signals.

As you can see the "event_frame_started" is '1' for 1 FPGA cycle. Is that too short for the PS to detect?

ILA.jpg
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tmaintz
Adventurer
Adventurer
845 Views
Registered: ‎12-26-2016

I didn't know about the AXI Interrupt Controller. After a few mistakes with the core I give it some more tries. Nevertheless this core didn't generated an interrupt on the single sided output for the Zynq PL-PS IRq input. I guess this is because of a misconfiguration.

 

I'll keep you updated.

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tmaintz
Adventurer
Adventurer
975 Views
Registered: ‎12-26-2016

The AXI Interrupt Controler is the answer ;)

Setting this Core to level detect mode helps me out.

 

Sorry for answering my own posts!

 

Greetings,
Thomas

View solution in original post

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