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Visitor
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Registered: ‎07-16-2020

ZCU102 - PS Address Layout

Hi all,

can somebody perhaps point me to a document that describes the address layout seen by the APU (A53 cores) in the Zynq ZCU102 platform?

I know there is a DDR4 in the PS side, and what I suspect that 2 GBs of it occupy the address range from 0x00000000 to 0x7FFFFFFF in the physical address space (and another 2 GBs are mapped in an address range that can no longer be indexed with only 32 bits).

Anyway, I would appreciate a document that gives me the details about it.

Best Regards, Leonardo.


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Registered: ‎07-16-2020

Found it:
https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf

Thats the document... in case anyone else needs it.
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