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Newbie
Newbie
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Registered: ‎08-27-2020

ZCU104(MPSOC) but pure logic design (PL side) example?

Hello,

I'm using ZCU104 board (because it is relatively not expensive) but I actually only want to use the logic side (PL side), for digital design verification purpose. Everything will be reside in PL side and nothing in PS side shall be used.

I wonder if there's any documentation, application note or examples that can help guiding me in this specific way of using MPSOC chip?

 

Thanks and Best Regards,

Yours,

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Registered: ‎01-07-2013

I doubt you will need an example design. If you have used Vivado in the past for non-MPSoC devices the design process is the same for the PL portion of the MPSoC. You do your HDL design, add your constraints file, build, and program the FPGA over JTAG.

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Newbie
Newbie
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Registered: ‎08-27-2020

My design inside PL is supposed to be a tiny processor. Everything the FPGA board is powered up, I wish it can automatically load bit stream for PL and start execution from my self-maintained processor, while other parts of the MPSoc (PS) won't has any side effect to the PL region.

Manually using JTAG mode might work, but I do concern about the MPSoc boot flow will affect my desired way of starting up from PL directly. 

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Registered: ‎01-07-2013

If you want the PL to be programmed out of flash on the ZCU104 the easiest way is through the PS. The First Stage Boot Loader (FSBL) will come up and program the PL. After that it doesn't matter what the PS does. It will be running but won't be interacting with the PL. Your custom processor in the PL won't even know it's there.

If you program the PL over JTAG it will be manual. You will have to do it every time. If that's acceptable you won't have to do anything with the PS. Again, once you program the PL over JTAG the PS will still be running (It might crash) but it doesn't matter. Your PL design will continue to run the same as if it were on any other FPGA board.

If I were going to go the FSBL route this is how I would do it. I would get the ZCU104's TRD. I would open the Vivado design and strip out everything except the Zynq in the block diagram. Then I would build your design the way you would if you were targeting any FPGA board. Run implementation. Then export the XSA file and include the bitstream.

Next step is petalinux.You will have to install petalinux. Then run the setup script from the petalinux installation directory:

source ./settings.sh

Start with the TRD's petalinux BSP. To inflate it you run this command:

petalinux-create -t project -s <PATH TO TRD BSP FILE>

Then from the inflated petalinux project you have to import the XSA that you created. You do that with this command:

petalinux-config --get-hw-description=<PATH TO DIRECTORY CONTAINING XSA> --silentconfig

Then you build the petalinux project:

petalinux-build

Finally package everything you will need to copy to the SD Card:

petalinux-package --boot --force --fsbl ./images/linux/zynqmp_fsbl.elf --fpga ./images/linux/system.bit --u-boot ./images/linux/u-boot.elf

You will have to copy BOOT.BIN and image.ub over to the boot partition of the SD Card. There is a Linux file system that you would copy too if you were going to use the PS. But BOOT.BIN and image.ub will be sufficient if you only want the PL to be programmed and don't care about bringing Linux up on the PS.

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Newbie
Newbie
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Registered: ‎08-27-2020

Hi Dustin,

Thanks a lot for your detailed instruction. It is very clear and helpful.

Best Regards

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Newbie
Newbie
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Registered: ‎08-27-2020

I have worked all the way out booting from either QSPI or SD card. In my case, PetaLinux is not necessary. All I need to do is to generate an boot image (.bin or .msc) by combining a FSBL(first stage boot loader) of AP core and a bitstream for PL. Then that boot image can be programmed to QSPI (bin or msc format) or SD card (bin format only).

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Registered: ‎01-07-2013

Sorry, is that a question or a statement? It is true that you do not need Linux but the Petalinux tools will generate the FSBL and PM Firmware, etc...

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Newbie
Newbie
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Registered: ‎08-27-2020

I guess more like a statement. Vitis 2020 tool is able to provide the needed FSBL and you can generate image using that FSBL and your bit file.
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Registered: ‎01-07-2013

That is true. I personally find Vitis to be much more difficult to use than Petalinux. Petalinux is a much more mature tool.

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