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ramyan
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Registered: ‎01-05-2021

ZCU104 PL IRQ - GIC register overview

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I would like know the register overview of the PL IRQ's (IRQ signals from PL to GICs) in the ZCU104 board.

"ug1085-zynq-ultrascale-trm.pdf" details the IRQ number for PL_PS_Group0 IRQ as 121:128 and PL_PS_Group1 IRQ as 136:142. It also details the base address of the GIC400.GICD as "0xF901_0000" and GIC400.GICC as "0xF902_0000" for a processor without security extensions. However, detailed information of the offset address of the PL IRQ status, mask, enable, disable registers are not specified.

I have referred the "Arm® Generic Interrupt Controller Architecture version 2.0" documentation to understand the detailed register overview.

1. Is the "GICC_PMR" register with offset address "0x0004" corresponds to the mask register of PL IRQ?
2. Can APU access the "GICC_PMR" register and other GIC registers?

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abouassi
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Registered: ‎03-25-2019

Hi @ramyan,

>However, detailed information of the offset address of the PL IRQ status, mask, enable, disable registers are not specified
You can find the needed details on UG1087. Open the link and search for GICP2 and GICP3:

abouassi_0-1612783581398.png

 

Best regards,
Abdallah
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abouassi
Moderator
Moderator
294 Views
Registered: ‎03-25-2019

Hi @ramyan,

>However, detailed information of the offset address of the PL IRQ status, mask, enable, disable registers are not specified
You can find the needed details on UG1087. Open the link and search for GICP2 and GICP3:

abouassi_0-1612783581398.png

 

Best regards,
Abdallah
-------------------------------------------------------------------------------
Please don't forget to reply, kudo and accept as a solution

View solution in original post

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