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bsarbb
Observer
Observer
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Registered: ‎03-11-2021

ZCU104 PS I2C ISR[DATA] rising in write case.

Hello,

I am trying to understand that, In which situations, ISR[DATA] bit rise in I2C write case ? 
In my case, I am trying to send data over I2C and waiting for ISR[COMP] to rise but before that ISR[DATA] rising. Should I ignore ISR[DATA] slightly in write case ?

Further details:
I2C controller operates in master mode and the speed of the communication is 100 kHz. Only one slave exists in communication line and finally I am working on ZCU104 development board.

From programming point of view,
I am initializing I2C peripheral in master mode, enabling 7 bit addressing mode, enabling ack. Then I am mapping I2C interrupt to related processor and enable it. This is all I do in init phase.
In transfer phase, first I am setting the clock related registers. Then I am clearing FIFO by setting CLR_FIFO bit in CR register and putting I2C peripheral to master transmitter mode again. Then I am starting transfer with writing address to address register. Lastly I am enabling COMP,DATA, NACK, TO, RX_OVR, ARB_LOST interrupts and waiting for interrupt flags. Thats all I do. 

I read this document https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/PS-IIC-and-AXI-IIC-debug-techniques/ba-p/1135303@pvenugo  says DATA bit in ISR register triggered at every 14 bytes reading data. But even though I put the I2C controller to master transmitter mode, this bit still triggered.

I think this problem maybe caused by one of the following:
1- I misunderstand the meaning of the DATA. (TRM dont explain the details of the behaviour of this bit.)
2- My initialization phase or transfer phase missing something. (If so, could you please suggest me a solution ? )
3- Hardware side has bug.

Thanks.

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venui
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Registered: ‎04-09-2019

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bsarbb
Observer
Observer
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Registered: ‎03-11-2021

Hello @venui,

I followed your suggestion but writer says "The DATA bit has a trigger in the ISR register for every 14 bytes of reading data" in FAQ section. The behaviour is not like that in my case. Although I run IIC in master transmitter mode, the DATA bit still triggered. This is what I am asking. Is this behaviour expected, I mean do you encounter with this kind of behaviour ? or Is this unexpected behaviour ?  

Regards,

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venui
Moderator
Moderator
167 Views
Registered: ‎04-09-2019

Hi @bsarbb  It is applicable for both reception and transmission.

Regards,

Venu

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