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Adventurer
Adventurer
736 Views
Registered: ‎11-10-2017

ZCU111 RFDC Baremetal Example and Tile Issue

Hello, When I try to execute the read_write example or self_test example present in github (link: https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/rfdc/examples/xrfdc_read_write_example.c) it executes fine, but I do not see any wave or output in my oscilloscope. I created my own Block in vivado, I made sure the ADC and DAC are enabled and Enable PLL is checked. I am not clear on why there is no sine wave or any output signal detected in the Oscilloscope. If some one has a working example on how to do this in XSDK (baremetal) approach, please share with me. (I do not want to generate the signal using the RF User Interface , but via baremetal application)

 

I also have got ADC 225 and DAC 229 enabled in my design which corresponds to Tile 1. But the example that i used from github, they uses Tile=0x00. The code still works fine but if I change it to Tile = 0x01, the code fails. Not clear on why it is happening like this. Please help me understand on the tile concept also.

 

Thanks, Vish

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Xilinx Employee
Xilinx Employee
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Registered: ‎02-01-2008

I presume you are using zcu111 and your 'created my own Block' is creating a waveform over axis.

A few things to look at:

  • are you configuring the zcu111 clock generators with the correct freq required by the RFDC block via the calls into xrfdc_clk.c
  • depending on the freq selected I've seen issues where some of the clk generator registers are configured wrong. For example ClockingLmx entry for 1.474560Gbps has two register values I've had to change
  • use xsct to read the reset status registers. For DAC7 I read offset 0x800C and for ADC0 I read offset 0x1400C. This registers should contain 0xF. If they are stuck around a value of 0x3 0r 0x4, then the rfdc block is configured for a clock that is different than what is fed to it

I have attached a design that plays URAM/BRAM contents to the DAC and captures ADC to URAM/BRAM. You can use xsct to read/write your waveforms.

Regarding tile 0 vs tile 1 issue, I noticed this a while ago and created a CR so hopefully it makes it into the next version of tools. There were functions that would check if the tile was enabled, access it, then move to the next tile. So if tile 0 was not enabled, no further tiles would get processed. Tile 0 needs to be enable anyway if you are using MTS.

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Adventurer
Adventurer
577 Views
Registered: ‎11-10-2017

Hi @johnmcd 

Could please take a look at the following thread 

https://forums.xilinx.com/t5/Evaluation-Boards/RfSoc-ZCU111-DAC-implementation-with-Baremetal/m-p/1007304#M23714

 

I was able make some progress but stuck with waveform generation.

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